From 40275217569502977caad9da0ecc43ea77c06148 Mon Sep 17 00:00:00 2001 From: Renze Nicolai Date: Thu, 21 Dec 2017 15:26:49 +0100 Subject: mainboard/nf81-t56n-lf: Add temperature sensor configuration This patch adds the temperature sensor type device tree setting, configured to be the default value as stated in the Fintek f71869ad datasheet on page 60. bit 7-4: reserved (0) bit 3: T3_MODE 1 (default) = BJT, 0 = thermistor bit 2: T2_MODE 1 (default) = BJT, 0 = thermistor bit 1: T1_MODE 1 (default) = BJT, 0 = thermistor bit 0: reserved (0) This results in a default value of 0x0E This change is needed to make sure behaviour does not change after applying change 22935 which adds the temperature sensor type devicetree configuration option Change-Id: I42980988267621def6576f771f1d8a853500e867 Signed-off-by: Renze Nicolai Reviewed-on: https://review.coreboot.org/22966 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 0db35ce8ee..dd442b2e3b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -68,6 +68,7 @@ chip northbridge/amd/agesa/family14/root_complex register "hwm_fan1_seg2_speed_count" = "0x0e" register "hwm_fan1_seg3_speed_count" = "0x07" register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_temp_sensor_type" = "0x0E" # default value # # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c -- cgit v1.2.3