From 4177db52a29b28a023a9ae84ed76c40ed6ce4daf Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 5 Feb 2014 14:55:26 -0600 Subject: baytrail/rambi: spi, charger, and audio updates baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie --- src/mainboard/google/rambi/Makefile.inc | 1 + src/mainboard/google/rambi/acpi/dptf.asl | 30 +++++++---- src/mainboard/google/rambi/acpi/mainboard.asl | 62 +++++++++------------- src/mainboard/google/rambi/chromeos.c | 11 ++++ src/mainboard/google/rambi/devicetree.cb | 4 +- src/mainboard/google/rambi/mainboard.c | 2 - src/mainboard/google/rambi/mainboard_smi.c | 12 ----- src/mainboard/google/rambi/romstage.c | 13 ++--- src/mainboard/google/rambi/w25q64.c | 74 +++++++++++++++++++++++++++ 9 files changed, 138 insertions(+), 71 deletions(-) create mode 100644 src/mainboard/google/rambi/w25q64.c (limited to 'src/mainboard') diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 572baaac89..52e1855e40 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -24,5 +24,6 @@ ramstage-y += chromeos.c ramstage-y += gpio.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += irqroute.c +ramstage-y += w25q64.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 51237dc576..975c9396f1 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,9 +1,9 @@ -#define DPTF_CPU_PASSIVE 60 -#define DPTF_CPU_CRITICAL 70 +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 60 +#define DPTF_TSR0_PASSIVE 48 #define DPTF_TSR0_CRITICAL 70 #define DPTF_TSR1_SENSOR_ID 2 @@ -13,28 +13,40 @@ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 60 +#define DPTF_TSR2_PASSIVE 55 #define DPTF_TSR2_CRITICAL 70 -#undef DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, #endif /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) /* Include Baytrail DPTF */ diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 1f5b7a1551..f0f7a4c178 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -25,8 +25,8 @@ Scope (\_SB) { Device (LID0) { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) { Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) Return (\LIDS) @@ -35,15 +35,18 @@ Scope (\_SB) Device (PWRB) { - Name(_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) } + /* Wake device for touchpad */ Device (TPAD) { Name (_HID, EisaId ("PNP0C0E")) Name (_UID, 1) + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - Name (_CRS, ResourceTemplate() + Name (RBUF, ResourceTemplate() { Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -51,25 +54,23 @@ Scope (\_SB) } }) - Method (_STA) + Method (_CRS) { - /* Disable if I2C1 is in ACPI mode */ - If (LEqual (\S1EN, 1)) { - Return (0x0) - } Else { - Return (0xF) + /* Only return interrupt if I2C1 is PCI mode */ + If (LEqual (\S1EN, 0)) { + Return (^RBUF) } } - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) } + /* Wake device for touchscreen */ Device (TSCR) { Name (_HID, EisaId ("PNP0C0E")) Name (_UID, 2) + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - Name (_CRS, ResourceTemplate() + Name (RBUF, ResourceTemplate() { Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -77,17 +78,13 @@ Scope (\_SB) } }) - Method (_STA) + Method (_CRS) { - /* Disable if I2C6 is in ACPI mode */ - If (LEqual (\S6EN, 1)) { - Return (0x0) - } Else { - Return (0xF) + /* Only return interrupt if I2C6 is PCI mode */ + If (LEqual (\S6EN, 0)) { + Return (^RBUF) } } - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) } } @@ -107,7 +104,7 @@ Scope (\_SB.I2C1) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C1", // ResourceSource + "\\_SB.I2C1", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -131,7 +128,6 @@ Scope (\_SB.I2C1) Device (ATPA) { Name (_HID, "ATML0000") - Name (_CID, EisaId ("PNP0C0E")) Name (_DDN, "Atmel Touchpad") Name (_UID, 2) Name (ISTP, 1) /* Touchpad */ @@ -143,7 +139,7 @@ Scope (\_SB.I2C1) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C1", // ResourceSource + "\\_SB.I2C1", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -162,14 +158,11 @@ Scope (\_SB.I2C1) /* Allow device to power off in S0 */ Name (_S0W, 4) - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) } Device (ETPA) { Name (_HID, "ELAN0000") - Name (_CID, EisaId ("PNP0C0E")) Name (_DDN, "Elan Touchpad") Name (_UID, 3) Name (ISTP, 1) /* Touchpad */ @@ -181,7 +174,7 @@ Scope (\_SB.I2C1) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C1", // ResourceSource + "\\_SB.I2C1", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -200,8 +193,6 @@ Scope (\_SB.I2C1) /* Allow device to power off in S0 */ Name (_S0W, 4) - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) } } @@ -226,7 +217,7 @@ Scope (\_SB.I2C2) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C2", // ResourceSource + "\\_SB.I2C2", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -266,7 +257,7 @@ Scope (\_SB.I2C5) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C5", // ResourceSource + "\\_SB.I2C5", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -301,7 +292,7 @@ Scope (\_SB.I2C6) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C6", // ResourceSource + "\\_SB.I2C6", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -325,7 +316,6 @@ Scope (\_SB.I2C6) Device (ATSA) { Name (_HID, "ATML0001") - Name (_CID, EisaId ("PNP0C0E")) Name (_DDN, "Atmel Touchscreen") Name (_UID, 5) Name (ISTP, 0) /* TouchScreen */ @@ -337,7 +327,7 @@ Scope (\_SB.I2C6) ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode - "\_SB.I2C6", // ResourceSource + "\\_SB.I2C6", // ResourceSource ) Interrupt (ResourceConsumer, Edge, ActiveLow) { @@ -356,8 +346,6 @@ Scope (\_SB.I2C6) /* Allow device to power off in S0 */ Name (_S0W, 4) - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) } } diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 27af118852..0c3fe2a625 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -96,6 +96,17 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if defined(__PRE_RAM__) + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); } diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 79a2d229c0..95b2b3a398 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_freq" = "19" # 19.2MHz clock register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] # SD Card controller @@ -73,7 +73,7 @@ chip soc/intel/baytrail device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE - device pci 1b.0 off end # HDA + device pci 1b.0 on end # HDA device pci 1c.0 on end # PCIE_PORT1 device pci 1c.1 on end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3 diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 49e9ab56aa..f8c80aef9d 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -39,8 +39,6 @@ void mainboard_suspend_resume(void) { - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); } #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 09a858039d..f2bb7e97ad 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -126,21 +126,9 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0); } -#define APMC_FINALIZE 0xcb - -static int mainboard_finalized = 0; - int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { - case APMC_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: google_chromeec_set_smi_mask(0); /* Clear all pending events */ diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 48fe387bb5..7c505e73b3 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -42,12 +42,6 @@ static const uint32_t dual_channel_config = #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 -static inline void disable_internal_pull(int pad) -{ - const int pull_mask = ~(0xf << 7); - write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); -} - static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; @@ -55,9 +49,9 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) /* The ram_id[2:0] pullups on rambi are too large for the default 20K * pulldown on the pad. Therefore, disable the internal pull resistor to * read high values correctly. */ - disable_internal_pull(GPIO_SSUS_37_PAD); - disable_internal_pull(GPIO_SSUS_38_PAD); - disable_internal_pull(GPIO_SSUS_39_PAD); + ssus_disable_internal_pull(GPIO_SSUS_37_PAD); + ssus_disable_internal_pull(GPIO_SSUS_38_PAD); + ssus_disable_internal_pull(GPIO_SSUS_39_PAD); ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); @@ -85,6 +79,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) .mainboard = { .dram_type = DRAM_DDR3L, .dram_info_location = DRAM_INFO_SPD_MEM, + .weaker_odt_settings = 1, }, }; diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c new file mode 100644 index 0000000000..dbc26e4732 --- /dev/null +++ b/src/mainboard/google/rambi/w25q64.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +} -- cgit v1.2.3