From 58f68e80ec5f9f3d5cf65d6b9360030109b420e0 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Fri, 15 Jun 2018 15:50:32 -0700 Subject: mainboard/google/nocturne: Enable IPU3 Enable Image Processing Unit and CIO2 device that constitute IPU3. BUG=None TEST=Build and boot up into Nocturne platform and check with lspci. Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Signed-off-by: Lijian Zhao Signed-off-by: Tomasz Figa Reviewed-on: https://review.coreboot.org/27124 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 17bd3c0eb4..d8151431e4 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -40,8 +40,8 @@ chip soc/intel/skylake register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" - register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready - register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready + register "Cio2Enable" = "1" + register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" -- cgit v1.2.3