From 7223bfa47ea831fca634550ad7e7a534d0fe8ec9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 10 Oct 2020 16:37:44 +0530 Subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code Add required ASL files into dsdt.asl TEST=Dump and disassemble DSDT and verify all ACPI devices are present. Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/dsdt.asl | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 6163d01d3c..d4fb7a4273 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include DefinitionBlock( "dsdt.aml", @@ -11,5 +13,35 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { + #include + /* global NVS and variables */ + #include + + #include + + Device (\_SB.PCI0) { + #include + #include + #include + #include + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +#endif + + #include } -- cgit v1.2.3