From 92da206532598bd0cec91b2cddc7a1296400d728 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 13 May 2014 23:52:30 +1000 Subject: superio/winbond/w83627uhg: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Convert dependent board to generic winbond serial init. Note the clock function is actually invalid since it never enters into PNP config mode to twiddle the register. Further, 48MHz is the default (page 9 of data-sheet) and so romstage.c need not do anything to the clock rate hence why it presumably works with this invalid function. Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5725 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- src/mainboard/asrock/imb-a180/romstage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 5b64cf9c05..8ce496b652 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,7 +35,8 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" -#include "superio/winbond/w83627uhg/early_serial.c" +#include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) @@ -80,9 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); - /* Set w83627uhg to 48MHz and enable w83627uhg */ - w83627uhg_set_input_clk_sel(SERIAL_DEV, 0); - w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } -- cgit v1.2.3