From a081305729938448dc66ed2e9b2c48ef89ea4356 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 24 Apr 2014 11:43:00 -0500 Subject: rambi: align gpu pipea settings with the VBIOS In the normal mode case these settings aren't overwritten by the VBIOS because the VBIOS does not run. Therefore, the settings need to align with what the VBIOS programs so that there is a consistent panel power sequencing. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted. Noted settings set by firmware for both dev and normal mode match. Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/196822 Original-Reviewed-by: Marc Jones (cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803) Signed-off-by: Marc Jones Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf Reviewed-on: http://review.coreboot.org/7846 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Edward O'Callaghan --- src/mainboard/google/rambi/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 27dadca885..4f0a016cbe 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -41,9 +41,9 @@ chip soc/intel/baytrail # Enable PIPEA as DP_C register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "5" # 400ms - register "gpu_pipea_power_on_delay" = "2000" # 200ms - register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms -- cgit v1.2.3