From aa6a8fb9198acfe22fec944bc9484a800d689ff4 Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Tue, 29 Oct 2019 14:47:11 +0800 Subject: mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- src/mainboard/intel/saddlebrook/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 670a474865..ea3578550c 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -34,7 +34,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 5d69e52740..c2dd6f97cf 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -42,7 +42,7 @@ chip soc/intel/skylake register "Device4Enable" = "0" register "Heci3Enabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch -- cgit v1.2.3