From d738b1459788590e9ab21d09f32fbf2eca324412 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 16 Sep 2015 18:23:23 +0200 Subject: google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/veyron/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index c474bd652f..38a9ef64f8 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -85,4 +85,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON -- cgit v1.2.3