From dd4ef173f1082f670ad6302bf93d37cc57f8b043 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Nov 2018 14:57:17 -0800 Subject: mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOS We are seeing problems (interrupt storm) with using the same gpio for FP MCU wake and irq signals. Reverting back to using separate gpios for wake and irq until we resolve the issue. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Also, unlock from lock screen with fingerprint. Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/29665 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Vincent Wang --- src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/gpio.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index de00522f8c..49e35b27ed 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -455,7 +455,7 @@ chip soc/intel/skylake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D6_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" register "wake" = "GPE0_DW1_06" # GPP_D6 device spi 0 on end end # FPMCU diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index f48033af16..2c9b9325d0 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -421,12 +421,14 @@ static const struct pad_config fpmcu_gpio_table[] = { PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), + /* C8 : UART0_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D6 : ISH_I2C0_SCL ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D6, 20K_PU, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_ACPI_SCI(GPP_D6, 20K_PU, DEEP, INVERT), /* D17 : DMIC_CLK1 ==> NC */ PAD_CFG_NC(GPP_D17), }; -- cgit v1.2.3