From fada3e56c4d896bcbf41280f0d20ed7c72000890 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 27 Apr 2020 00:14:05 +0200 Subject: mb/asus/p8h61-m_pro: Fix function of pin 70 The board uses the pin for Deep S5, but the code was setting 3VSBSW. Change-Id: I81c865358002e6af500658efea851ab8c8202950 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 0ad35776a9..ce6acadb8e 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -90,7 +90,7 @@ chip northbridge/intel/sandybridge irq 0xe5 = 0x06 irq 0xe6 = 0x0c irq 0xe7 = 0x11 - irq 0xf0 = 0x20 + irq 0xf0 = 0x00 irq 0xf2 = 0x5d end device pnp 2e.b on # HWM, LED -- cgit v1.2.3