From fb93178f13c49c786ba142b119de9245eaf5b52b Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Fri, 20 May 2011 17:50:14 +0000 Subject: Correct amd persimmon romstage code for early SPI prefetch enable. Signed-off-by: Scott Duplichan Acked-by: Scott Duplichan git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/persimmon/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 1bcb0d1407..3f2aa10329 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (boot_cpu()) { __outdword (0xcf8, 0x8000a3b8); - __outdword (0xcfc, __indword (0xcfc) | 0 << 24); + __outdword (0xcfc, __indword (0xcfc) | 1 << 24); } // early enable of SPI 33 MHz fast mode read -- cgit v1.2.3