From fe2a4c1001dcb92947616213855feccf4495e479 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Mon, 9 Mar 2020 12:56:30 +0530 Subject: =?UTF-8?q?mb/google/drallion/variants/drallion:=20Set=20PCH=20The?= =?UTF-8?q?rmal=20Trip=20point=20to=2077=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Bora Guvendik --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d0006d64d7..60be8c9fab 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -175,6 +175,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { -- cgit v1.2.3