From 2b790f651230589fd66e8121745986b8a939b13b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Sep 2013 05:25:57 +0300 Subject: CBMEM AMD: Fix calls to set_top_of_ram_once() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can postpone the call to set_top_of_ram_once() outside the loops and make just one call instead. As set_top_of_ram() is now only called once, it is no longer necessary to check if high_tables_base was already set. Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/agesa/family10/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family12/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family14/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 ++++++++---------- 6 files changed, 48 insertions(+), 60 deletions(-) (limited to 'src/northbridge/amd/agesa') diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 602d473d73..1c7e5474d6 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -914,6 +914,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1036,11 +1037,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -1057,15 +1055,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 4c230f1cf2..42b4b3de59 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -590,6 +590,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -722,11 +723,8 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -743,16 +741,16 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fbf8e44064..7cc812bf59 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -575,6 +575,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -716,11 +717,8 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -737,16 +735,16 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index bdd69396bd..a8cc1ccb3c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -684,6 +684,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -807,11 +808,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -828,15 +826,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 736e634899..b55d52b997 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -671,6 +671,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -793,11 +794,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -815,15 +813,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 266319cef6..b8bba5025d 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,6 +677,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -799,11 +800,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -821,15 +819,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { -- cgit v1.2.3