From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/northbridge/amd/amdmct/amddefs.h | 36 ------------------------------------ 1 file changed, 36 deletions(-) (limited to 'src/northbridge/amd/amdmct/amddefs.h') diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 977fd9c959..1a442082ff 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -120,42 +120,6 @@ #define HTPHY_DIRECT_MAP 0x20000000 #define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF - -/* - * Various AMD MSRs - */ -#define CPUID_EXT_PM 0x80000007 -#define CPUID_MODEL 1 -#define MCG_CAP 0x00000179 - #define MCG_CTL_P 8 - #define MCA_BANKS_MASK 0xff -#define MC0_CTL 0x00000400 -#define MC0_STA (MC0_CTL + 1) -#define MC4_MISC0 0x00000413 -#define MC4_MISC1 0xC0000408 -#define MC4_MISC2 0xC0000409 -#define FS_Base 0xC0000100 -#define SYSCFG 0xC0010010 -#define HWCR 0xC0010015 -#define NB_CFG 0xC001001F -#define FidVidStatus 0xC0010042 -#define MC1_CTL_MASK 0xC0010045 -#define MC4_CTL_MASK 0xC0010048 -#define OSVW_ID_Length 0xC0010140 -#define OSVW_Status 0xC0010141 -#define CPUIDFEATURES 0xC0011004 -#define LS_CFG 0xC0011020 -#define IC_CFG 0xC0011021 -#define DC_CFG 0xC0011022 -#define BU_CFG 0xC0011023 -#define FP_CFG 0xC0011028 -#define DE_CFG 0xC0011029 -#define BU_CFG2 0xC001102A -#define BU_CFG3 0xC001102B -#define EX_CFG 0xC001102C -#define LS_CFG2 0xC001102D -#define IBS_OP_DATA3 0xC0011037 - /* * Processor package types */ -- cgit v1.2.3