From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 12 Oct 2018 10:54:30 +0200
Subject: cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

(limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 7421c18a69..b94c68c931 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -32,18 +32,19 @@
  * supported.
  */
 
-#include "mct_d_gcc.h"
-#include "mct_d.h"
 #include <console/console.h>
 #include <northbridge/amd/amdfam10/debug.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <reset.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <arch/acpi.h>
 #include <string.h>
 #include <device/dram/ddr3.h>
 #include "s3utils.h"
+#include "mct_d_gcc.h"
+#include "mct_d.h"
 
 static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
 					struct DCTStatStruc *pDCTstatA);
@@ -7770,7 +7771,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */
 
-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	lo |= 1 << ClLinesToNbDis;
 	_WRMSR(msr, lo, hi);
@@ -7786,7 +7787,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */
 
-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	if (!pDCTstat->ClToNB_flag)
 		lo &= ~(1<<ClLinesToNbDis);
@@ -7803,7 +7804,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */
 
-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi |= (1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -7818,7 +7819,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */
 
-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi &= ~(1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -8048,7 +8049,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 		return;
 	}
 
-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {		/* save the old value */
 		wrap32dis = 1;
@@ -8079,7 +8080,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 	}
 
 	if (!wrap32dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
-- 
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