From 33e5df3f25b4594c008788625cd405d988fc6e6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2013 10:51:34 +0300 Subject: Set PCI bus operations at buildtime for ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/lx/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/lx') diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index bde72a7776..33387f99e1 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -413,7 +413,6 @@ static void pci_domain_enable(device_t dev) // print_conf(); graphics_init(); - pci_set_method(dev); } static struct device_operations pci_domain_ops = { @@ -422,6 +421,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .scan_bus = pci_domain_scan_bus, .enable = pci_domain_enable, + .ops_pci_bus = pci_bus_default_ops, }; static void cpu_bus_init(device_t dev) -- cgit v1.2.3