From 2b9f5b5c121997e34743adf6fbe6b03676805404 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 26 Mar 2017 11:56:43 +0300 Subject: AGESA f16kb: Enable MRC cache equivalent fastboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Try restoring previous memory training results from SPI flash to improve raminit speed. Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20597 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/northbridge/amd/agesa/family16kb/state_machine.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 8457d832d7..00a7e85265 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -30,6 +30,13 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + AGESA_STATUS status; + + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + status = OemInitResume(&Post->MemConfig.MemContext); + if (AGESA_SUCCESS == status) + Post->MemConfig.MemRestoreCtl = 1; + } } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -- cgit v1.2.3