From 3e893bbed55f678155dfb58750376ad60a85e119 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 1 Jun 2018 06:32:20 +0300 Subject: intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/e7505/Makefile.inc | 2 ++ src/northbridge/intel/e7505/memmap.c | 14 +++++++------- 3 files changed, 10 insertions(+), 7 deletions(-) (limited to 'src/northbridge/intel/e7505') diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index d80ddf3efb..29613a92f4 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select RELOCATABLE_RAMSTAGE + select POSTCAR_STAGE config HW_SCRUBBER bool diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 57c870fde4..7f7c5e40aa 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -6,4 +6,6 @@ ramstage-y += memmap.c romstage-y += raminit.c romstage-y += debug.c romstage-y += memmap.c + +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 4a80608e81..48527fdd96 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -37,9 +37,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -59,8 +60,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } -- cgit v1.2.3