From b738913ce050cd5a61d902e7024d4881cdb1ae59 Mon Sep 17 00:00:00 2001 From: Dave Frodin Date: Fri, 1 May 2015 09:17:43 -0600 Subject: northbridge/intel/fsp_rangeley: Correct MMIO size setting The Rangeley chipset has the MMIO PCI config space feature enabled at 0xe0000000-0xefffffff. This is a 256MB space which covers all of config space. The ACPI table for this space only defines it as being 64MB. This change fixes that setting. Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e Signed-off-by: Dave Frodin Reviewed-on: http://review.coreboot.org/10047 Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/fsp_rangeley') diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl index 6a8c2e07a7..08dba89a71 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl @@ -30,7 +30,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000) + Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000) }) // Current Resource Settings -- cgit v1.2.3