From 128c104c4d3b91d3371b03840af460d776af819d Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 18 Nov 2016 09:29:03 -0700 Subject: nb/intel: Fix some spelling mistakes in comments and strings Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/gm45/bootblock.c') diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index fb40b9446a..10c64e9021 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -15,7 +15,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- cgit v1.2.3