From d53fd704f252ffde35c8bf2f2b16260edce76e79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Aug 2019 06:25:55 +0300 Subject: intel/smm/gen1: Use smm_subregion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I371ed41f485b3143e47f091681198d6674928897 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/memmap.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'src/northbridge/intel/gm45') diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 6e2f7037c2..7479a7834a 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -23,9 +23,9 @@ #include #include #include +#include #include #include -#include #include #include "gm45.h" @@ -84,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc) } } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -107,7 +107,7 @@ u32 northbridge_get_tseg_base(void) return tor; } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); return decode_tseg_size(esmramc) << 10; @@ -123,14 +123,10 @@ void *cbmem_top(void) return (void *) top_of_ram; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) -- cgit v1.2.3