From 0a4457ff44b10f22b711f64e88888c757fbedf32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 1 Aug 2019 20:29:14 +0300 Subject: lib/stage_cache: Refactor Kconfig options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/northbridge/intel/haswell/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb803d..dbf91bf60d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK -- cgit v1.2.3