From fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: northbridge/intel: Rename ram_calc.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/Makefile.inc | 6 ++-- src/northbridge/intel/haswell/memmap.c | 50 ++++++++++++++++++++++++++++++ src/northbridge/intel/haswell/ram_calc.c | 50 ------------------------------ 3 files changed, 53 insertions(+), 53 deletions(-) create mode 100644 src/northbridge/intel/haswell/memmap.c delete mode 100644 src/northbridge/intel/haswell/ram_calc.c (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ca1c04fa13..b9863367c9 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,14 +17,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c ramstage-y += minihd.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c @@ -37,6 +37,6 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c new file mode 100644 index 0000000000..3a63afcde6 --- /dev/null +++ b/src/northbridge/intel/haswell/memmap.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include "haswell.h" + +static uintptr_t smm_region_start(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignment. + */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c deleted file mode 100644 index 3a63afcde6..0000000000 --- a/src/northbridge/intel/haswell/ram_calc.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include "haswell.h" - -static uintptr_t smm_region_start(void) -{ - /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignment. - */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom & ~((1 << 20) - 1); -} - -void *cbmem_top(void) -{ - return (void *)smm_region_start(); -} - -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} -- cgit v1.2.3