From 7a95575b850c280e8496f3acafb5978d5c4c93bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 7 Jan 2020 12:18:24 +0200 Subject: asus/{p2b-x,p3b-f},intel/i440bx: Move mainboard_romstage_entry() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/i440bx/Makefile.inc | 1 + src/northbridge/intel/i440bx/raminit.c | 6 +++--- src/northbridge/intel/i440bx/raminit.h | 7 +------ src/northbridge/intel/i440bx/romstage.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 9 deletions(-) create mode 100644 src/northbridge/intel/i440bx/romstage.c (limited to 'src/northbridge/intel/i440bx') diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 355d9b2524..57025859d3 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -19,6 +19,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c romstage-y += raminit.c +romstage-y += romstage.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c romstage-y += memmap.c diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 08019880b7..597ba946b4 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -667,7 +667,7 @@ static void spd_enable_refresh(void) Public interface. -----------------------------------------------------------------------------*/ -void sdram_set_registers(void) +static void sdram_set_registers(void) { int i, max; uint8_t reg; @@ -977,7 +977,7 @@ static void set_dram_row_attributes(void) PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); } -void sdram_set_spd_registers(void) +static void sdram_set_spd_registers(void) { /* Setup DRAM row boundary registers and other attributes. */ set_dram_row_attributes(); @@ -993,7 +993,7 @@ void sdram_set_spd_registers(void) pci_write_config8(NB, DRAMT, 0x03); } -void sdram_enable(void) +static void sdram_enable(void) { int i; diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 347c1fecd7..1e9f25b8be 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -22,13 +22,8 @@ void enable_spd(void); void disable_spd(void); - -/* Function prototypes. */ -void sdram_set_registers(void); -void sdram_set_spd_registers(void); -void sdram_enable(void); -/* A merger of above functions */ void sdram_initialize(void); +void mainboard_enable_serial(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c new file mode 100644 index 0000000000..1dee03a984 --- /dev/null +++ b/src/northbridge/intel/i440bx/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void mainboard_romstage_entry(void) +{ + mainboard_enable_serial(); + console_init(); + + i82371eb_early_init(); + + sdram_initialize(); + cbmem_initialize_empty(); +} -- cgit v1.2.3