From fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: northbridge/intel: Rename ram_calc.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i440bx/Makefile.inc | 6 +- src/northbridge/intel/i440bx/memmap.c | 94 +++++++++++++++++++++++++++++++ src/northbridge/intel/i440bx/ram_calc.c | 94 ------------------------------- 3 files changed, 97 insertions(+), 97 deletions(-) create mode 100644 src/northbridge/intel/i440bx/memmap.c delete mode 100644 src/northbridge/intel/i440bx/ram_calc.c (limited to 'src/northbridge/intel/i440bx') diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index d41f65d755..2c503c63c1 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c -romstage-y += ram_calc.c +romstage-y += memmap.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c new file mode 100644 index 0000000000..495ca8682a --- /dev/null +++ b/src/northbridge/intel/i440bx/memmap.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Keith Hui + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i440bx.h" + +void *cbmem_top(void) +{ + /* Base of TSEG is top of usable DRAM */ + /* + * SMRAM - System Management RAM Control Register + * 0x72 + * [7:4] Not relevant to this function. + * [3:3] Global SMRAM Enable (G_SMRAME) + * [2:0] Hardwired to 010. + * + * ESMRAMC - Extended System Management RAM Control + * 0x73 + * [7:7] H_SMRAM_EN + * 1 = When G_SMRAME=1, High SMRAM space is enabled at + * 0x100A0000-0x100FFFFF and forwarded to DRAM address + * 0x000A0000-0x000FFFFF. + * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at + * 0x000A0000-0x000BFFFF. + * [6:3] Not relevant to this function. + * [2:1] TSEG Size (T_SZ) + * Selects the size of the TSEG memory block, if enabled. + * 00 = 128KiB + * 01 = 256KiB + * 10 = 512KiB + * 11 = 1MiB + * [0:0] TSEG_EN + * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to + * appear between DRAM address (TOM-) to TOM. + * + * Source: 440BX datasheet, pages 3-28 thru 3-29. + */ + unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + + int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; + /* T_SZ and TSEG_EN */ + int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; + if ((tseg & 0x1) && gsmrame) { + int tseg_size = 128 * KiB * (1 << (tseg >> 1)); + tom -= tseg_size; + } + return (void *)tom; +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache CBMEM region as WB. */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c deleted file mode 100644 index 495ca8682a..0000000000 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Keith Hui - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i440bx.h" - -void *cbmem_top(void) -{ - /* Base of TSEG is top of usable DRAM */ - /* - * SMRAM - System Management RAM Control Register - * 0x72 - * [7:4] Not relevant to this function. - * [3:3] Global SMRAM Enable (G_SMRAME) - * [2:0] Hardwired to 010. - * - * ESMRAMC - Extended System Management RAM Control - * 0x73 - * [7:7] H_SMRAM_EN - * 1 = When G_SMRAME=1, High SMRAM space is enabled at - * 0x100A0000-0x100FFFFF and forwarded to DRAM address - * 0x000A0000-0x000FFFFF. - * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at - * 0x000A0000-0x000BFFFF. - * [6:3] Not relevant to this function. - * [2:1] TSEG Size (T_SZ) - * Selects the size of the TSEG memory block, if enabled. - * 00 = 128KiB - * 01 = 256KiB - * 10 = 512KiB - * 11 = 1MiB - * [0:0] TSEG_EN - * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to - * appear between DRAM address (TOM-) to TOM. - * - * Source: 440BX datasheet, pages 3-28 thru 3-29. - */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; - - int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; - /* T_SZ and TSEG_EN */ - int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; - if ((tseg & 0x1) && gsmrame) { - int tseg_size = 128 * KiB * (1 << (tseg >> 1)); - tom -= tseg_size; - } - return (void *)tom; -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); -} -- cgit v1.2.3