From 128c104c4d3b91d3371b03840af460d776af819d Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 18 Nov 2016 09:29:03 -0700 Subject: nb/intel: Fix some spelling mistakes in comments and strings Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/i855/raminit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/northbridge/intel/i855') diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 43400ab068..3fd57656a9 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -484,7 +484,7 @@ static void sdram_enable(void) } /*----------------------------------------------------------------------------- -DIMM-independant configuration functions: +DIMM-independent configuration functions: -----------------------------------------------------------------------------*/ /** @@ -588,7 +588,7 @@ static void spd_set_dram_controller_mode(uint8_t dimm_mask) tRCD = spd_read_byte(dimm, SPD_tRCD); tRP = spd_read_byte(dimm, SPD_tRP); if (tRCD != tRP) { - PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); + PRINTK_DEBUG(" Disabling RAS lockout due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); controller_mode &= ~(1 << 15); } @@ -746,7 +746,7 @@ static void spd_set_dram_timing(uint8_t dimm_mask) /* FIXME: guess work starts here... * - * Intel refers to DQ turn-arround values for back to calculate the values, + * Intel refers to DQ turn-around values for back to calculate the values, * but i have no idea what this means */ @@ -900,7 +900,7 @@ static void northbridge_set_registers(void) /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); - /* Set the value for Programable Attribute Map Registers + /* Set the value for Programmable Attribute Map Registers * Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(NORTHBRIDGE, PAM0, 0x30); -- cgit v1.2.3