From 0c9630eeff6851d855179b3588fee87fce356d34 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Jan 2020 20:06:08 +0100 Subject: nb/intel/{i945,sandybridge}/bootblock.c: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38245 Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 38564bded1..1f20150ebb 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -26,7 +26,7 @@ void bootblock_early_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- cgit v1.2.3