From 29cc9eda2021a87396ef31a6fc81daff6fd1be7a Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Thu, 2 Jul 2009 18:56:24 +0000 Subject: Move the v3 resource allocator to v2. Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson Acked-by: Ronald G. Minnich Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/i945/northbridge.c | 32 +------------------------------- 1 file changed, 1 insertion(+), 31 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index b0ddbda7e4..c07a00c149 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -43,31 +43,6 @@ static void ram_resource(device_t dev, unsigned long index, unsigned long basek, IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -184,15 +159,10 @@ static void pci_domain_set_resources(device_t dev) #endif } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], 0, 0xff, max); /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. */ - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, -- cgit v1.2.3