From e4bc0f648067606841e5b24ed0bfe4d921838aec Mon Sep 17 00:00:00 2001 From: Peter Stuge Date: Fri, 1 Oct 2010 09:13:18 +0000 Subject: Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM Both chipsets use the src/northbridge/intel/i945 code but that code needs to know which chipset is actually used. Having separate NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed since code can test the NORTHBRIDGE_ option directly. Signed-off-by: Peter Stuge Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/i945/Kconfig | 28 +++++++++------------------- src/northbridge/intel/i945/raminit.c | 22 +++++++++------------- 2 files changed, 18 insertions(+), 32 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index cee1a8745d..6a8d376e60 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -17,38 +17,27 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config NORTHBRIDGE_INTEL_I945 +config NORTHBRIDGE_INTEL_I945GC bool select HAVE_DEBUG_RAM_SETUP +config NORTHBRIDGE_INTEL_I945GM + bool + select HAVE_DEBUG_RAM_SETUP + +if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM + config FALLBACK_VGA_BIOS_ID string default "8086,27a2" - depends on NORTHBRIDGE_INTEL_I945 - -choice - default I945GM - depends on NORTHBRIDGE_INTEL_I945 - help - Different i945 variants require slightly different setup. - -config I945GM - bool "i945GM (Mobile) chipset" - -config I945GC - bool "i945GC chipset" - -endchoice config CHANNEL_XOR_RANDOMIZATION bool default n - depends on NORTHBRIDGE_INTEL_I945 config OVERRIDE_CLOCK_DISABLE bool default n - depends on NORTHBRIDGE_INTEL_I945 help Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power @@ -59,8 +48,9 @@ config OVERRIDE_CLOCK_DISABLE config MAXIMUM_SUPPORTED_FREQUENCY int default 0 - depends on NORTHBRIDGE_INTEL_I945 help If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of. + +endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 50cab4929d..62cd193d04 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -90,7 +90,7 @@ static void sdram_dump_mchbar_registers(void) static int memclk(void) { int offset = 0; -#if CONFIG_I945GM +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { @@ -102,7 +102,7 @@ static int memclk(void) return -1; } -#if CONFIG_I945GM +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) static int fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -113,8 +113,7 @@ static int fsbclk(void) } return -1; } -#endif -#if CONFIG_I945GC +#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) static int fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -1045,7 +1044,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index) return nc; } -#if CONFIG_I945GM +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -1100,8 +1099,7 @@ static const u8 single_channel_strength_multiplier[] = { 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#endif -#if CONFIG_I945GC +#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -2155,7 +2153,7 @@ static void sdram_program_clock_crossing(void) /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG_I945GM +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2200,8 +2198,7 @@ static void sdram_program_clock_crossing(void) 0xffffffff, 0xffffffff, /* nonexistant */ }; -#endif -#if CONFIG_I945GC +#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2792,10 +2789,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) { u8 clocks[2] = { 0, 0 }; -#if CONFIG_I945GM +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #define CLOCKS_WIDTH 2 -#endif -#if CONFIG_I945GC +#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) -- cgit v1.2.3