From 9addda3c410041ea93ae5587d17460da9a9c312f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 22 Jul 2020 18:37:32 +0200
Subject: nb/intel/ironlake: Add Generic Non-Core register definitions

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/northbridge/intel/ironlake/ironlake.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/northbridge/intel/ironlake/ironlake.h')

diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 4f9db5b347..325de5b57f 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -52,6 +52,10 @@
  */
 #define QPI_NON_CORE		PCI_DEV(QUICKPATH_BUS, 0, 0)
 
+#define MAX_RTIDS		0x60
+#define DESIRED_CORES		0x80
+#define MIRROR_PORT_CTL		0xd0
+
 /*
  * SAD - System Address Decoder
  */
-- 
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