From 6f8b7df8ab69cd2be7d024dfbd7fbeb3a684c6b3 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 8 Oct 2016 18:42:46 +0200 Subject: cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An epic battle to fix Nehalem finally ended when we found an odd mask set in SMRR. This was caused by a wrong calculation of TSEG size. It was assumed that TSEG spans the whole space between TSEG base and GTT. This is wrong as TSEG base might have been aligned down. TEST: On X201, copied 1GiB from usb key to sd-card and verified. Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7 Found-by: Alexander Couzens, Nico Huber Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/16939 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexander Couzens Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/nehalem/northbridge.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'src/northbridge/intel/nehalem') diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 7f44272593..06c0a9655b 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -162,16 +162,11 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -void -northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +u32 northbridge_get_tseg_base(void) { - device_t dev; - u32 bgsm; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - *tsegmb = pci_read_config32(dev, TSEG) & ~1; - bgsm = pci_read_config32(dev, D0F0_GTT_BASE); - *tseg_size = bgsm - *tsegmb; + return pci_read_config32(dev, TSEG) & ~1; } static void mc_set_resources(device_t dev) -- cgit v1.2.3