From 4bdfebd4d88c1d84662cae3d11de1ee40f9e0017 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 9 Apr 2018 22:10:33 +0200 Subject: nb/intel/pineview: Enable and allocate 8M for TSEG TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/pineview.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/pineview/pineview.h') diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index a2cda84428..9873d4de81 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -62,7 +62,7 @@ #define REMAPBASE 0x98 #define REMAPLIMIT 0x9a #define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAM 0x9e /* Extended System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ #define TOM 0xa0 #define TOUUD 0xa2 -- cgit v1.2.3