From 089b9089c111da9175d87c4f2671ba8ebe353b4b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 27 May 2018 14:37:32 +0200 Subject: nb/intel: Use postcar_frame_add_romcache() Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/pineview/ram_calc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/northbridge/intel/pineview') diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index e98ad71881..fd893bc87a 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -118,8 +118,7 @@ void *setup_stack_and_mtrrs(void) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); -- cgit v1.2.3