From 2a0e998ec2d1625c214bf181189bd61ce425f0ed Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 14 Jan 2017 17:32:20 +0100 Subject: nb/intel/pineview: Make preallocated igd memory a cmos parameter Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/18142 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/pineview/early_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/pineview') diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 842ffa1e7a..e1cf95f298 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,6 +25,7 @@ #include #include #include +#include #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) @@ -45,7 +46,16 @@ static void early_graphics_setup(void) const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */ + + /* vram size from cmos option */ + if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) + reg8 = 0; /* 0 for 8MB */ + /* make sure no invalid setting is used */ + if (reg8 > 6) + reg8 = 0; + /* Select 1M GTT */ + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) + | ((reg8 + 3) << 4)); printk(BIOS_SPEW, "Set GFX clocks..."); reg16 = MCHBAR16(MCH_GCFGC); -- cgit v1.2.3