From ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Wed, 10 Feb 2016 01:36:25 +0100 Subject: Merge sandy/ivybridge romstage flow for MRC and non-MRC. Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Martin Roth --- src/northbridge/intel/sandybridge/raminit_mrc.c | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c') diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a370eccd31..162caf6107 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" @@ -279,3 +280,29 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } + +void perform_raminit(int s3resume) +{ + int cbmem_was_initted; + struct pei_data pei_data; + + /* Prepare USB controller early in S3 resume */ + if (!mainboard_should_reset_usb(s3resume)) + enable_usb_bar(); + + mainboard_fill_pei_data(&pei_data); + + post_code(0x3a); + pei_data.boot_mode = s3resume ? 2 : 0; + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(&pei_data); + cbmem_was_initted = !cbmem_recovery(s3resume); + if (!s3resume) + save_mrc_data(&pei_data); + + if (s3resume && !cbmem_was_initted) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } +} -- cgit v1.2.3