From 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 16 Mar 2020 23:17:32 +0100 Subject: nb/intel/sandybridge: Tidy up code and comments - Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_native.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/sandybridge/raminit_native.h') diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index ecf13cf1f8..60a5665ba9 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -18,8 +18,8 @@ #include "sandybridge.h" #include -/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ +/* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */ void read_spd(spd_raw_data *spd, u8 addr, bool id_only); void mainboard_get_spd(spd_raw_data *spd, bool id_only); -#endif /* RAMINIT_H */ +#endif /* RAMINIT_NATIVE_H */ -- cgit v1.2.3