From a2cc23169a81f669fa38ebf0f6b1393b06c17fda Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 15 May 2017 10:13:36 +0200 Subject: nb/intel/x4x: Rename a things that are not specific to DDR2 This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/x4x/x4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/x4x/x4x.h') diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index cc17ed6e91..f3b910f814 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -360,7 +360,7 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); -void raminit_ddr2(struct sysinfo *s, int fast_boot); +void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); u32 fsb2mhz(u32 speed); u32 ddr2mhz(u32 speed); -- cgit v1.2.3