From 64f6b71af5443ac4e1126dc5f5202a1bc8657b31 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:16:56 +0200 Subject: src/northbridge: Fix typo Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/x4x/ram_calc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/x4x') diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3b69..1f1c13f092 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -93,7 +93,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) -- cgit v1.2.3