From 66fa9e2865dc68fd3d89714138c8e0d27ff16819 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Fri, 26 Oct 2012 19:00:22 +0200 Subject: northbridge/sch: don't overwrite hightables with GPU / TSEG memory Without this, the hightables are placed just before the end of memory. However we might have the GPU memory located at the exact same spot, that is in the last 4 MiB. So without this patch, this area won't remain marked as "CONFIGURATION TABLES" within coreboot's memory table but becomes "RESERVED" because it is part of the PCI(2,0) device. Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160 Signed-off-by: Sebastian Andrzej Siewior Reviewed-on: http://review.coreboot.org/1627 Reviewed-by: Patrick Georgi Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/northbridge/intel/sch/northbridge.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 16ada2fa6c..fb3bff8492 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -188,7 +188,9 @@ static void pci_domain_set_resources(device_t dev) #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables. */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; + high_tables_base -= uma_memory_size; + high_tables_base -= tseg_memory_base; high_tables_size = HIGH_MEMORY_SIZE; #endif } -- cgit v1.2.3