From 67031a565b3179fa5a28282fc2e24b47d16003e8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 5 Feb 2018 19:08:03 +0100 Subject: cpu/intel/sandybridge: Put stage cache into TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/sandybridge/sandybridge.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index a3b4faad1d..46ebfc3df0 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -40,7 +40,8 @@ #define IVB_STEP_D0 (BASE_REV_IVB + 6) /* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 + +#define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ -- cgit v1.2.3