From 76cedd2c292352d7dbd45fab70ec272e476d0910 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Sat, 2 May 2020 10:24:23 -0700
Subject: acpi: Move ACPI table support out of arch/x86 (3/5)

This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/northbridge/intel/e7505/northbridge.c       | 2 +-
 src/northbridge/intel/gm45/acpi.c               | 4 ++--
 src/northbridge/intel/gm45/northbridge.c        | 2 +-
 src/northbridge/intel/gm45/romstage.c           | 2 +-
 src/northbridge/intel/haswell/acpi.c            | 2 +-
 src/northbridge/intel/haswell/northbridge.c     | 2 +-
 src/northbridge/intel/i945/acpi.c               | 4 ++--
 src/northbridge/intel/i945/northbridge.c        | 2 +-
 src/northbridge/intel/ironlake/northbridge.c    | 2 +-
 src/northbridge/intel/pineview/acpi.c           | 4 ++--
 src/northbridge/intel/pineview/northbridge.c    | 2 +-
 src/northbridge/intel/sandybridge/acpi.c        | 2 +-
 src/northbridge/intel/sandybridge/northbridge.c | 2 +-
 src/northbridge/intel/x4x/acpi.c                | 4 ++--
 src/northbridge/intel/x4x/northbridge.c         | 2 +-
 15 files changed, 19 insertions(+), 19 deletions(-)

(limited to 'src/northbridge/intel')

diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 03230a53ae..e8944669a3 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index bdd0ed0822..c81d21f0d0 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -3,8 +3,8 @@
 
 #include <types.h>
 #include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 5f6c8a1c4f..d566120827 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -8,7 +8,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cpu/intel/smm_reloc.h>
 
 #include "chip.h"
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 5b68a7398a..9bfb4e99bb 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -5,7 +5,7 @@
 #include <romstage_handoff.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cpu/x86/lapic.h>
 #include <arch/romstage.h>
 #include <northbridge/intel/gm45/gm45.h>
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f4d9d65421..a66847d6a9 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -3,7 +3,7 @@
 
 #include <types.h>
 #include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include "haswell.h"
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index f7c6883852..552f032de5 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -3,7 +3,7 @@
 
 #include <commonlib/helpers.h>
 #include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/haswell/haswell.h>
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index e1258e04aa..1c7eabcb57 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -2,8 +2,8 @@
 /* This file is part of the coreboot project. */
 
 #include <types.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include "i945.h"
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 3fd3db69df..c080d0cbd5 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -8,7 +8,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cpu/intel/smm_reloc.h>
 #include "i945.h"
 
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index c1ee207bf1..7384223c0d 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c
index 54c42cf481..cf91f1ea65 100644
--- a/src/northbridge/intel/pineview/acpi.c
+++ b/src/northbridge/intel/pineview/acpi.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpigen.h>
-#include <arch/acpi.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi.h>
 #include <device/device.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <types.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index b24356361f..af4bfb8ef5 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -8,7 +8,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/intel/smm_reloc.h>
 
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 77aa8149da..3ae44b8b36 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -4,7 +4,7 @@
 #include <types.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ea2a737c2c..e947bc5613 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c
index fb1ebab753..67fc93334b 100644
--- a/src/northbridge/intel/x4x/acpi.c
+++ b/src/northbridge/intel/x4x/acpi.c
@@ -3,8 +3,8 @@
 
 #include <types.h>
 #include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include "x4x.h"
 
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 054d2aa2ed..8aab1f63bd 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -8,7 +8,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
-- 
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