From a1f1714ca5bcef864d154676b48fc30fa459f8dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 15 Nov 2020 12:50:03 +0100 Subject: nb/intel/sandybridge: Clarify register write It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ef4ae455f8..0939fe6348 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1954,6 +1954,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5, -- cgit v1.2.3