From b236352281405c3a6860b51af8acfd2e78c45e78 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 18:40:50 +0100 Subject: sb/intel/i82801gx: Add a function to set up BAR This removes some of the sb code in the nb. Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/i945/early_init.c | 5 +---- src/northbridge/intel/pineview/early_init.c | 8 ++------ 2 files changed, 3 insertions(+), 10 deletions(-) (limited to 'src/northbridge/intel') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ee10fdccb6..a5bfe6f6a9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -159,11 +159,8 @@ static void i945_setup_bars(void) /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN); + i82801gx_setup_bars(); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 1638f0e15a..3a9df510b7 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -158,12 +158,8 @@ static void pineview_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */ - pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */ - pci_write_config32(LPC, 0x88, 0x007c0291); + + i82801gx_setup_bars(); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); printk(BIOS_DEBUG, " done.\n"); -- cgit v1.2.3