From 8301d8348a0848d56fdf4dbd76acd6bdcd3fc944 Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 07:07:33 +0000 Subject: second round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/via/cx700/Makefile.inc | 10 +- src/northbridge/via/cx700/agp.c | 91 ++++++ src/northbridge/via/cx700/cx700_agp.c | 91 ------ src/northbridge/via/cx700/cx700_early_serial.c | 102 ------- src/northbridge/via/cx700/cx700_early_smbus.c | 266 ----------------- src/northbridge/via/cx700/cx700_lpc.c | 308 -------------------- src/northbridge/via/cx700/cx700_registers.h | 46 --- src/northbridge/via/cx700/cx700_reset.c | 26 -- src/northbridge/via/cx700/cx700_sata.c | 160 ----------- src/northbridge/via/cx700/cx700_usb.c | 56 ---- src/northbridge/via/cx700/cx700_vga.c | 210 -------------- src/northbridge/via/cx700/early_serial.c | 102 +++++++ src/northbridge/via/cx700/early_smbus.c | 266 +++++++++++++++++ src/northbridge/via/cx700/lpc.c | 308 ++++++++++++++++++++ src/northbridge/via/cx700/raminit.c | 2 +- src/northbridge/via/cx700/registers.h | 46 +++ src/northbridge/via/cx700/reset.c | 26 ++ src/northbridge/via/cx700/sata.c | 160 +++++++++++ src/northbridge/via/cx700/usb.c | 56 ++++ src/northbridge/via/cx700/vga.c | 210 ++++++++++++++ src/northbridge/via/vx800/Makefile.inc | 4 +- src/northbridge/via/vx800/early_serial.c | 101 +++++++ src/northbridge/via/vx800/early_smbus.c | 251 ++++++++++++++++ src/northbridge/via/vx800/ide.c | 265 +++++++++++++++++ src/northbridge/via/vx800/lpc.c | 377 +++++++++++++++++++++++++ src/northbridge/via/vx800/raminit.c | 4 +- src/northbridge/via/vx800/vx800_early_serial.c | 101 ------- src/northbridge/via/vx800/vx800_early_smbus.c | 251 ---------------- src/northbridge/via/vx800/vx800_ide.c | 265 ----------------- src/northbridge/via/vx800/vx800_lpc.c | 377 ------------------------- 30 files changed, 2269 insertions(+), 2269 deletions(-) create mode 100644 src/northbridge/via/cx700/agp.c delete mode 100644 src/northbridge/via/cx700/cx700_agp.c delete mode 100644 src/northbridge/via/cx700/cx700_early_serial.c delete mode 100644 src/northbridge/via/cx700/cx700_early_smbus.c delete mode 100644 src/northbridge/via/cx700/cx700_lpc.c delete mode 100644 src/northbridge/via/cx700/cx700_registers.h delete mode 100644 src/northbridge/via/cx700/cx700_reset.c delete mode 100644 src/northbridge/via/cx700/cx700_sata.c delete mode 100644 src/northbridge/via/cx700/cx700_usb.c delete mode 100644 src/northbridge/via/cx700/cx700_vga.c create mode 100644 src/northbridge/via/cx700/early_serial.c create mode 100644 src/northbridge/via/cx700/early_smbus.c create mode 100644 src/northbridge/via/cx700/lpc.c create mode 100644 src/northbridge/via/cx700/registers.h create mode 100644 src/northbridge/via/cx700/reset.c create mode 100644 src/northbridge/via/cx700/sata.c create mode 100644 src/northbridge/via/cx700/usb.c create mode 100644 src/northbridge/via/cx700/vga.c create mode 100644 src/northbridge/via/vx800/early_serial.c create mode 100644 src/northbridge/via/vx800/early_smbus.c create mode 100644 src/northbridge/via/vx800/ide.c create mode 100644 src/northbridge/via/vx800/lpc.c delete mode 100644 src/northbridge/via/vx800/vx800_early_serial.c delete mode 100644 src/northbridge/via/vx800/vx800_early_smbus.c delete mode 100644 src/northbridge/via/vx800/vx800_ide.c delete mode 100644 src/northbridge/via/vx800/vx800_lpc.c (limited to 'src/northbridge/via') diff --git a/src/northbridge/via/cx700/Makefile.inc b/src/northbridge/via/cx700/Makefile.inc index f67cc147a2..b833013790 100644 --- a/src/northbridge/via/cx700/Makefile.inc +++ b/src/northbridge/via/cx700/Makefile.inc @@ -17,10 +17,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += cx700_reset.c +ramstage-y += reset.c ramstage-y += northbridge.c -driver-y += cx700_agp.c -driver-y += cx700_lpc.c -driver-y += cx700_sata.c -driver-y += cx700_vga.c +driver-y += agp.c +driver-y += lpc.c +driver-y += sata.c +driver-y += vga.c diff --git a/src/northbridge/via/cx700/agp.c b/src/northbridge/via/cx700/agp.c new file mode 100644 index 0000000000..0166ee135a --- /dev/null +++ b/src/northbridge/via/cx700/agp.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */ + +static void agp_bridge_init(device_t dev) +{ + + device_t north_dev; + u8 reg8; + north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); + + pci_write_config8(north_dev, 0xa0, 0x1); // Enable CPU Direct Access Frame Buffer + + pci_write_config8(north_dev, 0xa2, 0x4a); + + reg8 = pci_read_config8(north_dev, 0xc0); + reg8 |= 0x1; + pci_write_config8(north_dev, 0xc0, reg8); + + /* + * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer + * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b + */ + north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0); + reg8 = pci_read_config8(north_dev, 0xb5); + reg8 |= 0x3; + pci_write_config8(north_dev, 0xb5, reg8); + pci_write_config8(north_dev, 0x94, 0x20); + pci_write_config8(north_dev, 0x13, 0xd0); + + pci_write_config16(dev, 0x4, 0x0007); + + pci_write_config8(dev, 0x19, 0x01); + pci_write_config8(dev, 0x1a, 0x01); + pci_write_config8(dev, 0x1c, 0xe0); + pci_write_config8(dev, 0x1d, 0xe0); + pci_write_config16(dev, 0x1e, 0xa220); + + pci_write_config16(dev, 0x20, 0xdd00); + pci_write_config16(dev, 0x22, 0xdef0); + pci_write_config16(dev, 0x24, 0xa000); + pci_write_config16(dev, 0x26, 0xbff0); + + pci_write_config8(dev, 0x3e, 0x0c); + pci_write_config8(dev, 0x40, 0x8b); + pci_write_config8(dev, 0x41, 0x43); + pci_write_config8(dev, 0x42, 0x62); + pci_write_config8(dev, 0x43, 0x44); + pci_write_config8(dev, 0x44, 0x34); +} + +static void cx700_noop(device_t dev) +{ +} + +static struct device_operations agp_bridge_operations = { + .read_resources = cx700_noop, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = agp_bridge_init, + .scan_bus = pci_scan_bridge, +}; + +static const struct pci_driver agp_bridge_driver __pci_driver = { + .ops = &agp_bridge_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xb198, +}; diff --git a/src/northbridge/via/cx700/cx700_agp.c b/src/northbridge/via/cx700/cx700_agp.c deleted file mode 100644 index 0166ee135a..0000000000 --- a/src/northbridge/via/cx700/cx700_agp.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */ - -static void agp_bridge_init(device_t dev) -{ - - device_t north_dev; - u8 reg8; - north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); - - pci_write_config8(north_dev, 0xa0, 0x1); // Enable CPU Direct Access Frame Buffer - - pci_write_config8(north_dev, 0xa2, 0x4a); - - reg8 = pci_read_config8(north_dev, 0xc0); - reg8 |= 0x1; - pci_write_config8(north_dev, 0xc0, reg8); - - /* - * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer - * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b - */ - north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0); - reg8 = pci_read_config8(north_dev, 0xb5); - reg8 |= 0x3; - pci_write_config8(north_dev, 0xb5, reg8); - pci_write_config8(north_dev, 0x94, 0x20); - pci_write_config8(north_dev, 0x13, 0xd0); - - pci_write_config16(dev, 0x4, 0x0007); - - pci_write_config8(dev, 0x19, 0x01); - pci_write_config8(dev, 0x1a, 0x01); - pci_write_config8(dev, 0x1c, 0xe0); - pci_write_config8(dev, 0x1d, 0xe0); - pci_write_config16(dev, 0x1e, 0xa220); - - pci_write_config16(dev, 0x20, 0xdd00); - pci_write_config16(dev, 0x22, 0xdef0); - pci_write_config16(dev, 0x24, 0xa000); - pci_write_config16(dev, 0x26, 0xbff0); - - pci_write_config8(dev, 0x3e, 0x0c); - pci_write_config8(dev, 0x40, 0x8b); - pci_write_config8(dev, 0x41, 0x43); - pci_write_config8(dev, 0x42, 0x62); - pci_write_config8(dev, 0x43, 0x44); - pci_write_config8(dev, 0x44, 0x34); -} - -static void cx700_noop(device_t dev) -{ -} - -static struct device_operations agp_bridge_operations = { - .read_resources = cx700_noop, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = agp_bridge_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver agp_bridge_driver __pci_driver = { - .ops = &agp_bridge_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0xb198, -}; diff --git a/src/northbridge/via/cx700/cx700_early_serial.c b/src/northbridge/via/cx700/cx700_early_serial.c deleted file mode 100644 index 3f5020f670..0000000000 --- a/src/northbridge/via/cx700/cx700_early_serial.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Enable the serial devices on the VIA CX700 - */ - -#include - -static void cx700_writepnpaddr(u8 val) -{ - outb(val, 0x2e); - outb(val, 0xeb); -} - -static void cx700_writepnpdata(u8 val) -{ - outb(val, 0x2f); - outb(val, 0xeb); -} - -static void cx700_writesiobyte(u16 reg, u8 val) -{ - outb(val, reg); -} - -static void cx700_writesioword(u16 reg, u16 val) -{ - outw(val, reg); -} - -static void enable_cx700_serial(void) -{ - outb(6, 0x80); - - // WTH? - outb(0x03, 0x22); - - // Set UART1 I/O Base Address - pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e); - - // UART1 Enable - pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10); - - // turn on pnp - cx700_writepnpaddr(0x87); - cx700_writepnpaddr(0x87); - // now go ahead and set up com1. - // set address - cx700_writepnpaddr(0x7); - cx700_writepnpdata(0x2); - // enable serial out - cx700_writepnpaddr(0x30); - cx700_writepnpdata(0x1); - // serial port 1 base address (FEh) - cx700_writepnpaddr(0x60); - cx700_writepnpdata(0xfe); - // serial port 1 IRQ (04h) - cx700_writepnpaddr(0x70); - cx700_writepnpdata(0x4); - // serial port 1 control - cx700_writepnpaddr(0xf0); - cx700_writepnpdata(0x2); - // turn of pnp - cx700_writepnpaddr(0xaa); - - // XXX This part should be fully taken care of by - // src/pc80/serial.c:uart_init - - // set up reg to set baud rate. - cx700_writesiobyte(0x3fb, 0x80); - // Set 115 kb - cx700_writesioword(0x3f8, 1); - // Set 9.6 kb - // cx700_writesioword(0x3f8, 12) - // now set no parity, one stop, 8 bits - cx700_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - cx700_writesiobyte(0x3fc, 3); - // Enable interrupts - cx700_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - cx700_writesiobyte(0x3f8, 48); - - outb(7, 0x80); -} diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c deleted file mode 100644 index 4766e59a29..0000000000 --- a/src/northbridge/via/cx700/cx700_early_smbus.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// other bioses use this, too: -#define SMBUS_IO_BASE 0x0500 - -#define SMBHSTSTAT SMBUS_IO_BASE + 0x0 -#define SMBSLVSTAT SMBUS_IO_BASE + 0x1 -#define SMBHSTCTL SMBUS_IO_BASE + 0x2 -#define SMBHSTCMD SMBUS_IO_BASE + 0x3 -#define SMBXMITADD SMBUS_IO_BASE + 0x4 -#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5 -#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6 - -#define SMBBLKDAT SMBUS_IO_BASE + 0x7 -#define SMBSLVCTL SMBUS_IO_BASE + 0x8 -#define SMBTRNSADD SMBUS_IO_BASE + 0x9 -#define SMBSLVDATA SMBUS_IO_BASE + 0xa -#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe -#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf - -/* Define register settings */ -#define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ - -#define SMBUS_TIMEOUT (100*1000*10) - -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 - -#define SMBUS_DELAY() outb(0x80, 0x80) - -/* Debugging macros. */ -#if CONFIG_DEBUG_SMBUS -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) -#else -#define PRINT_DEBUG(x) -#define PRINT_DEBUG_HEX16(x) -#endif - -/* Internal functions */ -#if CONFIG_DEBUG_SMBUS -static void smbus_print_error(unsigned char host_status_register, int loops) -{ - /* Check if there actually was an error */ - if (host_status_register == 0x00 || host_status_register == 0x40 || - host_status_register == 0x42) - return; - print_err("SMBus Error: "); - print_err_hex8(host_status_register); - - print_err("\n"); - if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\n"); - } - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } -} -#endif - -static void smbus_wait_until_ready(void) -{ - int loops; - - loops = 0; - - /* Yes, this is a mess, but it's the easiest way to do it */ - while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { - SMBUS_DELAY(); - ++loops; - } -#if CONFIG_DEBUG_SMBUS - /* Some systems seem to have a flakey SMBus. No need to spew a lot of - * errors on those, once we know that SMBus access is principally - * working. - */ - smbus_print_error(inb(SMBHSTSTAT), loops); -#endif -} - -static void smbus_reset(void) -{ - outb(HOST_RESET, SMBHSTSTAT); -} - -/* Public functions */ -static void set_ics_data(unsigned char dev, int data, char len) -{ - //int i; - smbus_reset(); - /* clear host data port */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* read to reset block transfer counter */ - inb(SMBHSTCTL); - - /* fill blocktransfer array */ - if (dev == 0xd2) { - //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; - outb(0x0d, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0x3f, SMBBLKDAT); - outb(0xcd, SMBBLKDAT); - outb(0x7f, SMBBLKDAT); - outb(0xbf, SMBBLKDAT); - outb(0x1a, SMBBLKDAT); - outb(0x2a, SMBBLKDAT); - outb(0x01, SMBBLKDAT); - outb(0x0f, SMBBLKDAT); - outb(0x0b, SMBBLKDAT); - outb(0x80, SMBBLKDAT); - outb(0x8d, SMBBLKDAT); - outb(0x9b, SMBBLKDAT); - } else { - //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; - outb(0x08, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0x3f, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - } - - //for (i=0; i < len; i++) - // outb(data[i],SMBBLKDAT); - - outb(dev, SMBXMITADD); - outb(0, SMBHSTCMD); - outb(len, SMBHSTDAT0); - outb(0x74, SMBHSTCTL); - - SMBUS_DELAY(); - - smbus_wait_until_ready(); - - smbus_reset(); - -} - -static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm, - unsigned int offset) -{ - unsigned int val, addr; - - smbus_reset(); - - /* clear host data port */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* Fetch the SMBus address of the SPD ROM from - * the ctrl struct in romstage.c in case they are at - * non-standard positions. - * SMBus Address shifted by 1 - */ - addr = (ctrl->channel0[dimm]) << 1; - - outb(addr | 0x1, SMBXMITADD); - outb(offset, SMBHSTCMD); - outb(0x48, SMBHSTCTL); - - SMBUS_DELAY(); - - smbus_wait_until_ready(); - - val = inb(SMBHSTDAT0); - smbus_reset(); - return val; -} - -static void enable_smbus(void) -{ - device_t dev; - - /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location, - * no need to probe. - */ - dev = PCI_DEV(0, 17, 0); - - /* SMBus Clock Select: Divider fof 14.318MHz */ - pci_write_config8(dev, 0x94, 0x20); - - /* SMBus I/O Base, enable SMBus */ - pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); - - /* SMBus Clock from 128K Source, Enable SMBus Host Controller */ - pci_write_config8(dev, 0xd2, 0x05); - - /* Enable I/O decoding */ - pci_write_config16(dev, 0x04, 0x0003); - - /* Setup clock chips */ - set_ics_data(0xd2, 0, 14); - set_ics_data(0xd4, 0, 9); -} - -/* Debugging Function */ -#if CONFIG_DEBUG_SMBUS -static void dump_spd_data(const struct mem_controller *ctrl) -{ - int dimm, offset, regs; - unsigned int val; - - for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { - print_debug("SPD Data for DIMM "); - print_debug_hex8(dimm); - print_debug("\n"); - - val = get_spd_data(ctrl, dimm, 0); - if (val == 0xff) { - regs = 256; - } else if (val == 0x80) { - regs = 128; - } else { - print_debug("No DIMM present\n"); - regs = 0; - } - for (offset = 0; offset < regs; offset++) { - print_debug(" Offset "); - print_debug_hex8(offset); - print_debug(" = 0x"); - print_debug_hex8(get_spd_data(ctrl, dimm, offset)); - print_debug("\n"); - } - } -} -#else -#define dump_spd_data(ctrl) -#endif diff --git a/src/northbridge/via/cx700/cx700_lpc.c b/src/northbridge/via/cx700/cx700_lpc.c deleted file mode 100644 index 77ab97c145..0000000000 --- a/src/northbridge/via/cx700/cx700_lpc.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ACPI_IO_BASE 0x400 -#define HPET_ADDR 0xfe800000UL - -static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 }; - -static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' }; -static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' }; -static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' }; -static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' }; - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char irqs[4]; - int i; - for (i = 0; i < 4; i++) - irqs[i] = pci_irqs[pin[i] - 'A']; - - return irqs; -} - -static void pci_routing_fixup(struct device *dev) -{ - printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev); - - /* set up PCI IRQ routing */ - pci_write_config8(dev, 0x55, pci_irqs[0] << 4); - pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4)); - pci_write_config8(dev, 0x57, pci_irqs[3] << 4); - - /* Assigning IRQs */ - printk(BIOS_DEBUG, "Setting up USB interrupts.\n"); - pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins)); - - printk(BIOS_DEBUG, "Setting up VGA interrupts.\n"); - pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins)); - - printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n"); - pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins)); - // more? - - printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n"); - pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins)); -} - -/* - * Set up the power management capabilities directly into ACPI mode. This - * avoids having to handle any System Management Interrupts (SMI's) which I - * can't figure out how to do !!!! - */ - -static void setup_pm(device_t dev) -{ - /* Debounce LID and PWRBTN# Inputs for 16ms. */ - pci_write_config8(dev, 0x80, 0x20); - - /* Set ACPI base address to IO ACPI_IO_BASE */ - pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1); - - /* set ACPI irq to 9 */ - pci_write_config8(dev, 0x82, 0x49); - - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x609a); - - /* SMI output level to low, 7.5us throttle clock */ - pci_write_config8(dev, 0x8d, 0x18); - - /* GP Timer Control 1s */ - pci_write_config8(dev, 0x93, 0x88); - - /* Power Well */ - pci_write_config8(dev, 0x94, 0x20); // 0x20?? - - /* 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - */ - pci_write_config8(dev, 0x95, 0xc0); // 0xc1?? - - /* Disable GP2 & GP3 Timer */ - pci_write_config8(dev, 0x98, 0); - - /* GP2 Timer Counter */ - pci_write_config8(dev, 0x99, 0xfb); - /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); - - /* Multi Function Select 1 */ - pci_write_config8(dev, 0xe4, 0x00); - - /* Multi Function Select 2 */ - pci_write_config8(dev, 0xe5, 0x41); //?? - - /* Enable ACPI access (and setup like award) */ - pci_write_config8(dev, 0x81, 0x84); - - /* Clear status events. */ - outw(0xffff, ACPI_IO_BASE + 0x00); - outw(0xffff, ACPI_IO_BASE + 0x20); - outw(0xffff, ACPI_IO_BASE + 0x28); - outl(0xffffffff, ACPI_IO_BASE + 0x30); - - /* Disable SCI on GPIO. */ - outw(0x0, ACPI_IO_BASE + 0x22); - - /* Disable SMI on GPIO. */ - outw(0x0, ACPI_IO_BASE + 0x24); - - /* Disable all global enable SMIs. */ - outw(0x0, ACPI_IO_BASE + 0x2a); - - /* All SMI off, both IDE buses ON, PSON rising edge. */ - outw(0x0, ACPI_IO_BASE + 0x2c); - - /* Primary activity SMI disable. */ - outl(0x0, ACPI_IO_BASE + 0x34); - - /* GP timer reload on none. */ - outl(0x0, ACPI_IO_BASE + 0x38); - - /* Disable extended IO traps. */ - outb(0x0, ACPI_IO_BASE + 0x42); - - /* SCI is generated for RTC/pwrBtn/slpBtn. */ - outw(0x0001, ACPI_IO_BASE + 0x04); - - /* Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, ACPI_IO_BASE + 0x11); -} - -static void cx700_set_lpc_registers(struct device *dev) -{ - unsigned char enables; - - printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n"); - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); - - /* DMA Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - /* I/O recovery time */ - pci_write_config8(dev, 0x4c, 0x44); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* Enable SM dynamic clock gating */ - pci_write_config8(dev, 0x5b, 0x01); - - /* Set Read Pass Write Control Enable */ - pci_write_config8(dev, 0x48, 0x0c); - - /* Set SM Misc Control: Enable Internal APIC . */ - enables = pci_read_config8(dev, 0x58); - enables |= 1 << 6; - pci_write_config8(dev, 0x58, enables); - enables = pci_read_config8(dev, 0x4d); - enables |= 1 << 3; - pci_write_config8(dev, 0x4d, enables); - - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - /* enable KBC configuration */ - pci_write_config8(dev, 0x51, 0x1f); - - /* enable serial irq */ - pci_write_config8(dev, 0x52, 0x9); - - /* dma */ - pci_write_config8(dev, 0x53, 0x00); - - // Power management setup - setup_pm(dev); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - - /* Enable HPET timer */ - pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8)); - -} - -static void cx700_read_resources(device_t dev) -{ - struct resource *res; - - /* Make sure we call our childrens set/enable functions - these - * are not called unless this device has a resource to set. - */ - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x400UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void cx700_set_resources(device_t dev) -{ - struct resource *resource; - resource = find_resource(dev, 1); - resource->flags |= IORESOURCE_STORED; - pci_dev_set_resources(dev); -} - -static void cx700_enable_resources(device_t dev) -{ - /* Enable SuperIO decoding */ - pci_dev_enable_resources(dev); -} - -static void cx700_lpc_init(struct device *dev) -{ - cx700_set_lpc_registers(dev); - -#if CONFIG_IOAPIC -#define IO_APIC_ID 2 - setup_ioapic(IO_APIC_ADDR, IO_APIC_ID); -#endif - - /* Initialize interrupts */ - pci_routing_fixup(dev); - /* make sure interupt controller is configured before keyboard init */ - setup_i8259(); - - /* Start the Real Time Clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Initialize keyboard controller */ - pc_keyboard_init(0); -} - -static struct device_operations cx700_lpc_ops = { - .read_resources = cx700_read_resources, - .set_resources = cx700_set_resources, - .enable_resources = cx700_enable_resources, - .init = &cx700_lpc_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &cx700_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0x8324, -}; diff --git a/src/northbridge/via/cx700/cx700_registers.h b/src/northbridge/via/cx700/cx700_registers.h deleted file mode 100644 index b63984f67f..0000000000 --- a/src/northbridge/via/cx700/cx700_registers.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ -#define SCRATCH_REG_BASE 0xd0 -#define SCRATCH_RANK_0 0xd0 -#define SCRATCH_RANK_1 0xd1 -#define SCRATCH_RANK_2 0xd2 -#define SCRATCH_RANK_3 0xd3 -#define SCRATCH_DIMM_NUM 0xd4 -#define SCRATCH_RANK_NUM 0xd5 -#define SCRATCH_RANK_MAP 0xd6 -#define SCRATCH_DRAM_FREQ 0xd7 -#define SCRATCH_DRAM_NB_ODT 0xd8 -#define SCRATCH_RANK0_SIZE_REG 0xe0 /* RxE0~RxE3 */ -#define SCRATCH_RANK0_MA_REG 0xe4 /* RxE4~RxE7 */ -#define SCRATCH_CHA_DQSI_LOW_REG 0xe8 -#define SCRATCH_CHA_DQSI_HIGH_REG 0xe9 -#define SCRATCH_ChA_DQSI_REG 0xea -#define SCRATCH_DRAM_256M_BIT 0xee -#define SCRATCH_FLAGS 0xef - -#define DDRII_666 0x5 -#define DDRII_533 0x4 -#define DDRII_400 0x3 -#define DDRII_333 0x2 -#define DDRII_266 0x1 -#define DDRII_200 0x0 - - diff --git a/src/northbridge/via/cx700/cx700_reset.c b/src/northbridge/via/cx700/cx700_reset.c deleted file mode 100644 index 83439881f6..0000000000 --- a/src/northbridge/via/cx700/cx700_reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -void hard_reset(void) -{ - outb((1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/northbridge/via/cx700/cx700_sata.c b/src/northbridge/via/cx700/cx700_sata.c deleted file mode 100644 index 993b05ad0a..0000000000 --- a/src/northbridge/via/cx700/cx700_sata.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -/* IDE specific bits */ -#define IDE_MODE_REG 0x09 -#define IDE0_NATIVE_MODE (1 << 0) -#define IDE1_NATIVE_MODE (1 << 2) - -/* These are default addresses */ -#define IDE0_DATA_ADDR 0x1f0 -#define IDE0_CONTROL_ADDR 0x3f4 -#define IDE1_DATA_ADDR 0x170 -#define IDE1_CONTROL_ADDR 0x370 - -#define BUS_MASTER_ADDR 0xfc00 - -#define CHANNEL_ENABLE_REG 0x40 -#define ENABLE_IDE0 (1 << 0) -#define ENABLE_IDE1 (1 << 1) - -/* TODO: better user configuration */ -#define DISABLE_SATA 0 - -static void sata_init(struct device *dev) -{ - u8 reg8; - - printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n"); - - /* Class IDE Disk, instead of RAID controller */ - reg8 = pci_read_config8(dev, 0x45); - reg8 &= 0x7f; /* Sub Class Write Protect off */ - pci_write_config8(dev, 0x45, reg8); - pci_write_config8(dev, 0x0a, 0x01); - reg8 |= 0x80; /* Sub Class Write Protect on */ - pci_write_config8(dev, 0x45, reg8); - -#if defined(DISABLE_SATA) && (DISABLE_SATA == 1) - printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n"); - /* Disable SATA channels */ - pci_write_config8(dev, 0x40, 0x00); -#else - pci_write_config8(dev, 0x40, 0x43); -#endif - - reg8 = pci_read_config8(dev, 0x6a); - reg8 |= 0x8; /* Mode Select set to Manual Mode */ - reg8 &= ~7; - reg8 |= 0x2; /* Manual setting to 50 ohm */ - - pci_write_config8(dev, 0x6a, reg8); - - reg8 = pci_read_config8(dev, 0x6b); - reg8 &= ~7; - reg8 |= 0x01; /* Autocomp of Termination */ - pci_write_config8(dev, 0x6b, reg8); - - /* Enable EIDE (secondary channel) even if SATA disabled */ - reg8 = pci_read_config8(dev, 0xc0); - reg8 |= 0x1; - pci_write_config8(dev, 0xc0, reg8); - - // Enable bus mastering, memory space acces, io space access - pci_write_config16(dev, 0x04, 0x0007); - - /* Set SATA base ports. */ - pci_write_config32(dev, 0x10, 0x01f1); - pci_write_config32(dev, 0x14, 0x03f5); - /* Set EIDE base ports. */ - pci_write_config32(dev, 0x18, 0x0171); - pci_write_config32(dev, 0x1c, 0x0375); - - /* SATA/EIDE Bus Master mode base address */ - pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); - - /* Enable read/write prefetch buffers */ - reg8 = pci_read_config8(dev, 0xc1); - reg8 |= 0x30; - pci_write_config8(dev, 0xc1, reg8); - - /* Set FIFO thresholds like */ - pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */ - - /* EIDE Sector Size */ - pci_write_config16(dev, 0xe8, 0x200); - - /* Some Miscellaneous Control */ - pci_write_config8(dev, 0x44, 0x7); - pci_write_config8(dev, 0x45, 0xaf); - pci_write_config8(dev, 0x46, 0x8); - - /* EIDE Configuration */ - reg8 = pci_read_config8(dev, 0xc4); - reg8 |= 0x10; - pci_write_config8(dev, 0xc4, reg8); - - pci_write_config8(dev, 0xc5, 0xc); - - /* Interrupt Line */ - reg8 = pci_read_config8(dev, 0x45); - reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */ - pci_write_config8(dev, 0x45, reg8); - - pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */ - - /* Set the drive timing control */ - pci_write_config16(dev, 0x48, 0x5d5d); - - /* Enable only compatibility mode. */ - reg8 = pci_read_config8(dev, 0x42); - reg8 &= ~0xa0; - pci_write_config8(dev, 0x42, reg8); - reg8 = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8); - - /* Support Staggered Spin-Up */ - reg8 = pci_read_config8(dev, 0xb9); - if ((reg8 & 0x8) == 0) { - printk(BIOS_DEBUG, "start OOB sequence on both drives\n"); - reg8 |= 0x30; - pci_write_config8(dev, 0xb9, reg8); - } -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .enable = 0, - .ops_pci = 0, -}; - -/* When the SATA controller is in IDE mode, the Device ID is 0x5324 */ -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0x5324, -}; diff --git a/src/northbridge/via/cx700/cx700_usb.c b/src/northbridge/via/cx700/cx700_usb.c deleted file mode 100644 index a85189477f..0000000000 --- a/src/northbridge/via/cx700/cx700_usb.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -static void usb_init(struct device *dev) -{ - u32 reg32; - u8 reg8; - - /* USB Specification says the device must be Bus Master */ - printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - - reg8 = pci_read_config8(dev, 0xca); - reg8 |= (1 << 0); - pci_write_config8(dev, 0xca, reg8); - - printk(BIOS_DEBUG, "done.\n"); -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver via_usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0x3038, -}; diff --git a/src/northbridge/via/cx700/cx700_vga.c b/src/northbridge/via/cx700/cx700_vga.c deleted file mode 100644 index 8fd94c71ef..0000000000 --- a/src/northbridge/via/cx700/cx700_vga.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cx700_registers.h" -#include "chip.h" -#include "northbridge.h" - -/* PCI Domain 1 Device 0 Function 0 */ - -#define SR_INDEX 0x3c4 -#define SR_DATA 0x3c5 -#define CRTM_INDEX 0x3b4 -#define CRTM_DATA 0x3b5 -#define CRTC_INDEX 0x3d4 -#define CRTC_DATA 0x3d5 - -static int via_cx700_int15_handler(struct eregs *regs) -{ - int res=-1; - u8 mem_speed; - -#define MEMORY_SPEED_66MHZ (0 << 4) -#define MEMORY_SPEED_100MHZ (1 << 4) -#define MEMORY_SPEED_133MHZ (1 << 4) -#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200 -#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266 -#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333 -#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400 -#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533 -#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667 - - const u8 memory_mapping[6] = { - MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ, - MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ, - MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ - }; - - printk(BIOS_DEBUG, "via_cx700_int15_handler\n"); - - switch(regs->eax & 0xffff) { - case 0x5f00: /* VGA POST Initialization Signal */ - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; - res = 0; - break; - - case 0x5f01: /* Software Panel Type Configuration */ - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; - // panel type = 2 = 1024 * 768 - regs->ecx = (regs->ecx & 0xffffff00 ) | 2; - res = 0; - break; - - case 0x5f27: /* Boot Device Selection */ - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; - - regs->ebx = 0x00000000; // 0 -> default - regs->ecx = 0x00000000; // 0 -> default - // TV Layout - default - regs->edx = (regs->edx & 0xffffff00) | 0; - res=0; - break; - - case 0x5f0b: /* Get Expansion Setting */ - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; - - regs->ecx = regs->ecx & 0xffffff00; // non-expansion - // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion - res=0; - break; - - case 0x5f0f: /* VGA Post Completion */ - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; - res=0; - break; - - case 0x5f18: - regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; -#define UMA_SIZE_8MB (3 << 0) -#define UMA_SIZE_16MB (4 << 0) -#define UMA_SIZE_32MB (5 << 0) - - regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB; - - mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ); - if (mem_speed > 5) - mem_speed = 5; - - regs->ebx |= memory_mapping[mem_speed]; - - res=0; - break; - - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); - break; - } - return res; -} - -#ifdef UNUSED_CODE -static void write_protect_vgabios(void) -{ - device_t dev; - - printk(BIOS_DEBUG, "write_protect_vgabios\n"); - - dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); - if (dev) - pci_write_config8(dev, 0x80, 0xff); - - dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0); - if (dev) - pci_write_config8(dev, 0x61, 0xff); -} -#endif - -static void vga_enable_console(void) -{ - /* Call VGA BIOS int10 function 0x4f14 to enable main console - * Epia-M does not always autosense the main console so forcing - * it on is good. - */ - - /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ - realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); -} - -static void vga_init(device_t dev) -{ - u8 reg8; - - mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler); - - //* - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x3e, 0x02); - pci_write_config8(dev, 0x0d, 0x40); - pci_write_config32(dev, 0x10, 0xa0000008); - pci_write_config32(dev, 0x14, 0xdd000000); - pci_write_config8(dev, 0x3c, 0x0b); - //*/ - - printk(BIOS_DEBUG, "Initializing VGA...\n"); - - pci_dev_init(dev); - - if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return; - - printk(BIOS_DEBUG, "Enable VGA console\n"); - vga_enable_console(); - - /* It's not clear if these need to be programmed before or after - * the VGA bios runs. Try both, clean up later */ - /* Set memory rate to 200MHz */ - outb(0x3d, CRTM_INDEX); - reg8 = inb(CRTM_DATA); - reg8 &= 0x0f; - reg8 |= (0x3 << 4); - outb(0x3d, CRTM_INDEX); - outb(reg8, CRTM_DATA); - - /* Set framebuffer size to 32mb */ - reg8 = (32 / 4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); -} - -static struct device_operations vga_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .ops_pci = 0, -}; - -static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0x3157, -}; diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c new file mode 100644 index 0000000000..3f5020f670 --- /dev/null +++ b/src/northbridge/via/cx700/early_serial.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Enable the serial devices on the VIA CX700 + */ + +#include + +static void cx700_writepnpaddr(u8 val) +{ + outb(val, 0x2e); + outb(val, 0xeb); +} + +static void cx700_writepnpdata(u8 val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + +static void cx700_writesiobyte(u16 reg, u8 val) +{ + outb(val, reg); +} + +static void cx700_writesioword(u16 reg, u16 val) +{ + outw(val, reg); +} + +static void enable_cx700_serial(void) +{ + outb(6, 0x80); + + // WTH? + outb(0x03, 0x22); + + // Set UART1 I/O Base Address + pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e); + + // UART1 Enable + pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10); + + // turn on pnp + cx700_writepnpaddr(0x87); + cx700_writepnpaddr(0x87); + // now go ahead and set up com1. + // set address + cx700_writepnpaddr(0x7); + cx700_writepnpdata(0x2); + // enable serial out + cx700_writepnpaddr(0x30); + cx700_writepnpdata(0x1); + // serial port 1 base address (FEh) + cx700_writepnpaddr(0x60); + cx700_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + cx700_writepnpaddr(0x70); + cx700_writepnpdata(0x4); + // serial port 1 control + cx700_writepnpaddr(0xf0); + cx700_writepnpdata(0x2); + // turn of pnp + cx700_writepnpaddr(0xaa); + + // XXX This part should be fully taken care of by + // src/pc80/serial.c:uart_init + + // set up reg to set baud rate. + cx700_writesiobyte(0x3fb, 0x80); + // Set 115 kb + cx700_writesioword(0x3f8, 1); + // Set 9.6 kb + // cx700_writesioword(0x3f8, 12) + // now set no parity, one stop, 8 bits + cx700_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + cx700_writesiobyte(0x3fc, 3); + // Enable interrupts + cx700_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + cx700_writesiobyte(0x3f8, 48); + + outb(7, 0x80); +} diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c new file mode 100644 index 0000000000..4766e59a29 --- /dev/null +++ b/src/northbridge/via/cx700/early_smbus.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// other bioses use this, too: +#define SMBUS_IO_BASE 0x0500 + +#define SMBHSTSTAT SMBUS_IO_BASE + 0x0 +#define SMBSLVSTAT SMBUS_IO_BASE + 0x1 +#define SMBHSTCTL SMBUS_IO_BASE + 0x2 +#define SMBHSTCMD SMBUS_IO_BASE + 0x3 +#define SMBXMITADD SMBUS_IO_BASE + 0x4 +#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5 +#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6 + +#define SMBBLKDAT SMBUS_IO_BASE + 0x7 +#define SMBSLVCTL SMBUS_IO_BASE + 0x8 +#define SMBTRNSADD SMBUS_IO_BASE + 0x9 +#define SMBSLVDATA SMBUS_IO_BASE + 0xa +#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe +#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + +#define SMBUS_TIMEOUT (100*1000*10) + +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +#define SMBUS_DELAY() outb(0x80, 0x80) + +/* Debugging macros. */ +#if CONFIG_DEBUG_SMBUS +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX16(x) +#endif + +/* Internal functions */ +#if CONFIG_DEBUG_SMBUS +static void smbus_print_error(unsigned char host_status_register, int loops) +{ + /* Check if there actually was an error */ + if (host_status_register == 0x00 || host_status_register == 0x40 || + host_status_register == 0x42) + return; + print_err("SMBus Error: "); + print_err_hex8(host_status_register); + + print_err("\n"); + if (loops >= SMBUS_TIMEOUT) { + print_err("SMBus Timout\n"); + } + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + /* This isn't a real error... */ + print_debug("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } +} +#endif + +static void smbus_wait_until_ready(void) +{ + int loops; + + loops = 0; + + /* Yes, this is a mess, but it's the easiest way to do it */ + while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { + SMBUS_DELAY(); + ++loops; + } +#if CONFIG_DEBUG_SMBUS + /* Some systems seem to have a flakey SMBus. No need to spew a lot of + * errors on those, once we know that SMBus access is principally + * working. + */ + smbus_print_error(inb(SMBHSTSTAT), loops); +#endif +} + +static void smbus_reset(void) +{ + outb(HOST_RESET, SMBHSTSTAT); +} + +/* Public functions */ +static void set_ics_data(unsigned char dev, int data, char len) +{ + //int i; + smbus_reset(); + /* clear host data port */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* read to reset block transfer counter */ + inb(SMBHSTCTL); + + /* fill blocktransfer array */ + if (dev == 0xd2) { + //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; + outb(0x0d, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0x3f, SMBBLKDAT); + outb(0xcd, SMBBLKDAT); + outb(0x7f, SMBBLKDAT); + outb(0xbf, SMBBLKDAT); + outb(0x1a, SMBBLKDAT); + outb(0x2a, SMBBLKDAT); + outb(0x01, SMBBLKDAT); + outb(0x0f, SMBBLKDAT); + outb(0x0b, SMBBLKDAT); + outb(0x80, SMBBLKDAT); + outb(0x8d, SMBBLKDAT); + outb(0x9b, SMBBLKDAT); + } else { + //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; + outb(0x08, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0x3f, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + } + + //for (i=0; i < len; i++) + // outb(data[i],SMBBLKDAT); + + outb(dev, SMBXMITADD); + outb(0, SMBHSTCMD); + outb(len, SMBHSTDAT0); + outb(0x74, SMBHSTCTL); + + SMBUS_DELAY(); + + smbus_wait_until_ready(); + + smbus_reset(); + +} + +static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm, + unsigned int offset) +{ + unsigned int val, addr; + + smbus_reset(); + + /* clear host data port */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Fetch the SMBus address of the SPD ROM from + * the ctrl struct in romstage.c in case they are at + * non-standard positions. + * SMBus Address shifted by 1 + */ + addr = (ctrl->channel0[dimm]) << 1; + + outb(addr | 0x1, SMBXMITADD); + outb(offset, SMBHSTCMD); + outb(0x48, SMBHSTCTL); + + SMBUS_DELAY(); + + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + smbus_reset(); + return val; +} + +static void enable_smbus(void) +{ + device_t dev; + + /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location, + * no need to probe. + */ + dev = PCI_DEV(0, 17, 0); + + /* SMBus Clock Select: Divider fof 14.318MHz */ + pci_write_config8(dev, 0x94, 0x20); + + /* SMBus I/O Base, enable SMBus */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); + + /* SMBus Clock from 128K Source, Enable SMBus Host Controller */ + pci_write_config8(dev, 0xd2, 0x05); + + /* Enable I/O decoding */ + pci_write_config16(dev, 0x04, 0x0003); + + /* Setup clock chips */ + set_ics_data(0xd2, 0, 14); + set_ics_data(0xd4, 0, 9); +} + +/* Debugging Function */ +#if CONFIG_DEBUG_SMBUS +static void dump_spd_data(const struct mem_controller *ctrl) +{ + int dimm, offset, regs; + unsigned int val; + + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + print_debug("SPD Data for DIMM "); + print_debug_hex8(dimm); + print_debug("\n"); + + val = get_spd_data(ctrl, dimm, 0); + if (val == 0xff) { + regs = 256; + } else if (val == 0x80) { + regs = 128; + } else { + print_debug("No DIMM present\n"); + regs = 0; + } + for (offset = 0; offset < regs; offset++) { + print_debug(" Offset "); + print_debug_hex8(offset); + print_debug(" = 0x"); + print_debug_hex8(get_spd_data(ctrl, dimm, offset)); + print_debug("\n"); + } + } +} +#else +#define dump_spd_data(ctrl) +#endif diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c new file mode 100644 index 0000000000..77ab97c145 --- /dev/null +++ b/src/northbridge/via/cx700/lpc.c @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ACPI_IO_BASE 0x400 +#define HPET_ADDR 0xfe800000UL + +static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 }; + +static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' }; +static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' }; +static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' }; +static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' }; + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char irqs[4]; + int i; + for (i = 0; i < 4; i++) + irqs[i] = pci_irqs[pin[i] - 'A']; + + return irqs; +} + +static void pci_routing_fixup(struct device *dev) +{ + printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev); + + /* set up PCI IRQ routing */ + pci_write_config8(dev, 0x55, pci_irqs[0] << 4); + pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4)); + pci_write_config8(dev, 0x57, pci_irqs[3] << 4); + + /* Assigning IRQs */ + printk(BIOS_DEBUG, "Setting up USB interrupts.\n"); + pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins)); + + printk(BIOS_DEBUG, "Setting up VGA interrupts.\n"); + pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins)); + + printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n"); + pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins)); + // more? + + printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n"); + pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins)); +} + +/* + * Set up the power management capabilities directly into ACPI mode. This + * avoids having to handle any System Management Interrupts (SMI's) which I + * can't figure out how to do !!!! + */ + +static void setup_pm(device_t dev) +{ + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to IO ACPI_IO_BASE */ + pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1); + + /* set ACPI irq to 9 */ + pci_write_config8(dev, 0x82, 0x49); + + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x609a); + + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* Power Well */ + pci_write_config8(dev, 0x94, 0x20); // 0x20?? + + /* 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + */ + pci_write_config8(dev, 0x95, 0xc0); // 0xc1?? + + /* Disable GP2 & GP3 Timer */ + pci_write_config8(dev, 0x98, 0); + + /* GP2 Timer Counter */ + pci_write_config8(dev, 0x99, 0xfb); + /* GP3 Timer Counter */ + //pci_write_config8(dev, 0x9a, 0x20); + + /* Multi Function Select 1 */ + pci_write_config8(dev, 0xe4, 0x00); + + /* Multi Function Select 2 */ + pci_write_config8(dev, 0xe5, 0x41); //?? + + /* Enable ACPI access (and setup like award) */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, ACPI_IO_BASE + 0x00); + outw(0xffff, ACPI_IO_BASE + 0x20); + outw(0xffff, ACPI_IO_BASE + 0x28); + outl(0xffffffff, ACPI_IO_BASE + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, ACPI_IO_BASE + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, ACPI_IO_BASE + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, ACPI_IO_BASE + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, ACPI_IO_BASE + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, ACPI_IO_BASE + 0x34); + + /* GP timer reload on none. */ + outl(0x0, ACPI_IO_BASE + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, ACPI_IO_BASE + 0x42); + + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + outw(0x0001, ACPI_IO_BASE + 0x04); + + /* Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, ACPI_IO_BASE + 0x11); +} + +static void cx700_set_lpc_registers(struct device *dev) +{ + unsigned char enables; + + printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n"); + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + // Map 4MB of FLASH into the address space +// pci_write_config8(dev, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* DMA Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf0; + pci_write_config8(dev, 0x42, enables); + + /* I/O recovery time */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* Enable SM dynamic clock gating */ + pci_write_config8(dev, 0x5b, 0x01); + + /* Set Read Pass Write Control Enable */ + pci_write_config8(dev, 0x48, 0x0c); + + /* Set SM Misc Control: Enable Internal APIC . */ + enables = pci_read_config8(dev, 0x58); + enables |= 1 << 6; + pci_write_config8(dev, 0x58, enables); + enables = pci_read_config8(dev, 0x4d); + enables |= 1 << 3; + pci_write_config8(dev, 0x4d, enables); + + /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + /* enable KBC configuration */ + pci_write_config8(dev, 0x51, 0x1f); + + /* enable serial irq */ + pci_write_config8(dev, 0x52, 0x9); + + /* dma */ + pci_write_config8(dev, 0x53, 0x00); + + // Power management setup + setup_pm(dev); + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev, 0x40, 0x54); + + /* Enable HPET timer */ + pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8)); + +} + +static void cx700_read_resources(device_t dev) +{ + struct resource *res; + + /* Make sure we call our childrens set/enable functions - these + * are not called unless this device has a resource to set. + */ + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void cx700_set_resources(device_t dev) +{ + struct resource *resource; + resource = find_resource(dev, 1); + resource->flags |= IORESOURCE_STORED; + pci_dev_set_resources(dev); +} + +static void cx700_enable_resources(device_t dev) +{ + /* Enable SuperIO decoding */ + pci_dev_enable_resources(dev); +} + +static void cx700_lpc_init(struct device *dev) +{ + cx700_set_lpc_registers(dev); + +#if CONFIG_IOAPIC +#define IO_APIC_ID 2 + setup_ioapic(IO_APIC_ADDR, IO_APIC_ID); +#endif + + /* Initialize interrupts */ + pci_routing_fixup(dev); + /* make sure interupt controller is configured before keyboard init */ + setup_i8259(); + + /* Start the Real Time Clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + /* Initialize keyboard controller */ + pc_keyboard_init(0); +} + +static struct device_operations cx700_lpc_ops = { + .read_resources = cx700_read_resources, + .set_resources = cx700_set_resources, + .enable_resources = cx700_enable_resources, + .init = &cx700_lpc_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &cx700_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x8324, +}; diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 5694ea31aa..d455768d96 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -21,7 +21,7 @@ #include #include #include -#include "cx700_registers.h" +#include "registers.h" /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h new file mode 100644 index 0000000000..b63984f67f --- /dev/null +++ b/src/northbridge/via/cx700/registers.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ +#define SCRATCH_REG_BASE 0xd0 +#define SCRATCH_RANK_0 0xd0 +#define SCRATCH_RANK_1 0xd1 +#define SCRATCH_RANK_2 0xd2 +#define SCRATCH_RANK_3 0xd3 +#define SCRATCH_DIMM_NUM 0xd4 +#define SCRATCH_RANK_NUM 0xd5 +#define SCRATCH_RANK_MAP 0xd6 +#define SCRATCH_DRAM_FREQ 0xd7 +#define SCRATCH_DRAM_NB_ODT 0xd8 +#define SCRATCH_RANK0_SIZE_REG 0xe0 /* RxE0~RxE3 */ +#define SCRATCH_RANK0_MA_REG 0xe4 /* RxE4~RxE7 */ +#define SCRATCH_CHA_DQSI_LOW_REG 0xe8 +#define SCRATCH_CHA_DQSI_HIGH_REG 0xe9 +#define SCRATCH_ChA_DQSI_REG 0xea +#define SCRATCH_DRAM_256M_BIT 0xee +#define SCRATCH_FLAGS 0xef + +#define DDRII_666 0x5 +#define DDRII_533 0x4 +#define DDRII_400 0x3 +#define DDRII_333 0x2 +#define DDRII_266 0x1 +#define DDRII_200 0x0 + + diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c new file mode 100644 index 0000000000..83439881f6 --- /dev/null +++ b/src/northbridge/via/cx700/reset.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +void hard_reset(void) +{ + outb((1 << 2) | (1 << 1), 0xcf9); +} diff --git a/src/northbridge/via/cx700/sata.c b/src/northbridge/via/cx700/sata.c new file mode 100644 index 0000000000..993b05ad0a --- /dev/null +++ b/src/northbridge/via/cx700/sata.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* IDE specific bits */ +#define IDE_MODE_REG 0x09 +#define IDE0_NATIVE_MODE (1 << 0) +#define IDE1_NATIVE_MODE (1 << 2) + +/* These are default addresses */ +#define IDE0_DATA_ADDR 0x1f0 +#define IDE0_CONTROL_ADDR 0x3f4 +#define IDE1_DATA_ADDR 0x170 +#define IDE1_CONTROL_ADDR 0x370 + +#define BUS_MASTER_ADDR 0xfc00 + +#define CHANNEL_ENABLE_REG 0x40 +#define ENABLE_IDE0 (1 << 0) +#define ENABLE_IDE1 (1 << 1) + +/* TODO: better user configuration */ +#define DISABLE_SATA 0 + +static void sata_init(struct device *dev) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n"); + + /* Class IDE Disk, instead of RAID controller */ + reg8 = pci_read_config8(dev, 0x45); + reg8 &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, 0x45, reg8); + pci_write_config8(dev, 0x0a, 0x01); + reg8 |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, 0x45, reg8); + +#if defined(DISABLE_SATA) && (DISABLE_SATA == 1) + printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n"); + /* Disable SATA channels */ + pci_write_config8(dev, 0x40, 0x00); +#else + pci_write_config8(dev, 0x40, 0x43); +#endif + + reg8 = pci_read_config8(dev, 0x6a); + reg8 |= 0x8; /* Mode Select set to Manual Mode */ + reg8 &= ~7; + reg8 |= 0x2; /* Manual setting to 50 ohm */ + + pci_write_config8(dev, 0x6a, reg8); + + reg8 = pci_read_config8(dev, 0x6b); + reg8 &= ~7; + reg8 |= 0x01; /* Autocomp of Termination */ + pci_write_config8(dev, 0x6b, reg8); + + /* Enable EIDE (secondary channel) even if SATA disabled */ + reg8 = pci_read_config8(dev, 0xc0); + reg8 |= 0x1; + pci_write_config8(dev, 0xc0, reg8); + + // Enable bus mastering, memory space acces, io space access + pci_write_config16(dev, 0x04, 0x0007); + + /* Set SATA base ports. */ + pci_write_config32(dev, 0x10, 0x01f1); + pci_write_config32(dev, 0x14, 0x03f5); + /* Set EIDE base ports. */ + pci_write_config32(dev, 0x18, 0x0171); + pci_write_config32(dev, 0x1c, 0x0375); + + /* SATA/EIDE Bus Master mode base address */ + pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); + + /* Enable read/write prefetch buffers */ + reg8 = pci_read_config8(dev, 0xc1); + reg8 |= 0x30; + pci_write_config8(dev, 0xc1, reg8); + + /* Set FIFO thresholds like */ + pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */ + + /* EIDE Sector Size */ + pci_write_config16(dev, 0xe8, 0x200); + + /* Some Miscellaneous Control */ + pci_write_config8(dev, 0x44, 0x7); + pci_write_config8(dev, 0x45, 0xaf); + pci_write_config8(dev, 0x46, 0x8); + + /* EIDE Configuration */ + reg8 = pci_read_config8(dev, 0xc4); + reg8 |= 0x10; + pci_write_config8(dev, 0xc4, reg8); + + pci_write_config8(dev, 0xc5, 0xc); + + /* Interrupt Line */ + reg8 = pci_read_config8(dev, 0x45); + reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */ + pci_write_config8(dev, 0x45, reg8); + + pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */ + + /* Set the drive timing control */ + pci_write_config16(dev, 0x48, 0x5d5d); + + /* Enable only compatibility mode. */ + reg8 = pci_read_config8(dev, 0x42); + reg8 &= ~0xa0; + pci_write_config8(dev, 0x42, reg8); + reg8 = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8); + + /* Support Staggered Spin-Up */ + reg8 = pci_read_config8(dev, 0xb9); + if ((reg8 & 0x8) == 0) { + printk(BIOS_DEBUG, "start OOB sequence on both drives\n"); + reg8 |= 0x30; + pci_write_config8(dev, 0xb9, reg8); + } +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = 0, + .ops_pci = 0, +}; + +/* When the SATA controller is in IDE mode, the Device ID is 0x5324 */ +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x5324, +}; diff --git a/src/northbridge/via/cx700/usb.c b/src/northbridge/via/cx700/usb.c new file mode 100644 index 0000000000..a85189477f --- /dev/null +++ b/src/northbridge/via/cx700/usb.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +static void usb_init(struct device *dev) +{ + u32 reg32; + u8 reg8; + + /* USB Specification says the device must be Bus Master */ + printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); + + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + reg8 = pci_read_config8(dev, 0xca); + reg8 |= (1 << 0); + pci_write_config8(dev, 0xca, reg8); + + printk(BIOS_DEBUG, "done.\n"); +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver via_usb_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3038, +}; diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c new file mode 100644 index 0000000000..91dd8649e9 --- /dev/null +++ b/src/northbridge/via/cx700/vga.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "registers.h" +#include "chip.h" +#include "northbridge.h" + +/* PCI Domain 1 Device 0 Function 0 */ + +#define SR_INDEX 0x3c4 +#define SR_DATA 0x3c5 +#define CRTM_INDEX 0x3b4 +#define CRTM_DATA 0x3b5 +#define CRTC_INDEX 0x3d4 +#define CRTC_DATA 0x3d5 + +static int via_cx700_int15_handler(struct eregs *regs) +{ + int res=-1; + u8 mem_speed; + +#define MEMORY_SPEED_66MHZ (0 << 4) +#define MEMORY_SPEED_100MHZ (1 << 4) +#define MEMORY_SPEED_133MHZ (1 << 4) +#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200 +#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266 +#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333 +#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400 +#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533 +#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667 + + const u8 memory_mapping[6] = { + MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ, + MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ, + MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ + }; + + printk(BIOS_DEBUG, "via_cx700_int15_handler\n"); + + switch(regs->eax & 0xffff) { + case 0x5f00: /* VGA POST Initialization Signal */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + res = 0; + break; + + case 0x5f01: /* Software Panel Type Configuration */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + // panel type = 2 = 1024 * 768 + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; + res = 0; + break; + + case 0x5f27: /* Boot Device Selection */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + + regs->ebx = 0x00000000; // 0 -> default + regs->ecx = 0x00000000; // 0 -> default + // TV Layout - default + regs->edx = (regs->edx & 0xffffff00) | 0; + res=0; + break; + + case 0x5f0b: /* Get Expansion Setting */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + + regs->ecx = regs->ecx & 0xffffff00; // non-expansion + // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion + res=0; + break; + + case 0x5f0f: /* VGA Post Completion */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + res=0; + break; + + case 0x5f18: + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; +#define UMA_SIZE_8MB (3 << 0) +#define UMA_SIZE_16MB (4 << 0) +#define UMA_SIZE_32MB (5 << 0) + + regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB; + + mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ); + if (mem_speed > 5) + mem_speed = 5; + + regs->ebx |= memory_mapping[mem_speed]; + + res=0; + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} + +#ifdef UNUSED_CODE +static void write_protect_vgabios(void) +{ + device_t dev; + + printk(BIOS_DEBUG, "write_protect_vgabios\n"); + + dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); + if (dev) + pci_write_config8(dev, 0x80, 0xff); + + dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0); + if (dev) + pci_write_config8(dev, 0x61, 0xff); +} +#endif + +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + +static void vga_init(device_t dev) +{ + u8 reg8; + + mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler); + + //* + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x3e, 0x02); + pci_write_config8(dev, 0x0d, 0x40); + pci_write_config32(dev, 0x10, 0xa0000008); + pci_write_config32(dev, 0x14, 0xdd000000); + pci_write_config8(dev, 0x3c, 0x0b); + //*/ + + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + + if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return; + + printk(BIOS_DEBUG, "Enable VGA console\n"); + vga_enable_console(); + + /* It's not clear if these need to be programmed before or after + * the VGA bios runs. Try both, clean up later */ + /* Set memory rate to 200MHz */ + outb(0x3d, CRTM_INDEX); + reg8 = inb(CRTM_DATA); + reg8 &= 0x0f; + reg8 |= (0x3 << 4); + outb(0x3d, CRTM_INDEX); + outb(reg8, CRTM_DATA); + + /* Set framebuffer size to 32mb */ + reg8 = (32 / 4); + outb(0x39, SR_INDEX); + outb(reg8, SR_DATA); +} + +static struct device_operations vga_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vga_init, + .ops_pci = 0, +}; + +static const struct pci_driver vga_driver __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3157, +}; diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index de6c491ebe..670a3e9550 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -20,8 +20,8 @@ driver-y += northbridge.c driver-y += vga.c -driver-y += vx800_lpc.c -driver-y += vx800_ide.c +driver-y += lpc.c +driver-y += ide.c chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c new file mode 100644 index 0000000000..f46341ff15 --- /dev/null +++ b/src/northbridge/via/vx800/early_serial.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/* + * Enable the serial devices on the VIA + */ +#include + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE 0x3f0 +#define SIO_DATA SIO_BASE+1 + +static void vx800_writepnpaddr(uint8_t val) +{ + outb(val, 0x2e); + outb(val, 0xeb); +} + +static void vx800_writepnpdata(uint8_t val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + +static void vx800_writesiobyte(uint16_t reg, uint8_t val) +{ + outb(val, reg); +} + +static void vx800_writesioword(uint16_t reg, uint16_t val) +{ + outw(val, reg); +} + +/* regs we use: 85, and the southbridge devfn is defined by the + mainboard + */ + +void enable_vx800_serial(void) +{ + outb(6, 0x80); + outb(0x03, 0x22); + + //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); + //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10); + + // turn on pnp + vx800_writepnpaddr(0x87); + vx800_writepnpaddr(0x87); + // now go ahead and set up com1. + // set address + vx800_writepnpaddr(0x7); + vx800_writepnpdata(0x2); + // enable serial out + vx800_writepnpaddr(0x30); + vx800_writepnpdata(0x1); + // serial port 1 base address (FEh) + vx800_writepnpaddr(0x60); + vx800_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + vx800_writepnpaddr(0x70); + vx800_writepnpdata(0x4); + // serial port 1 control + vx800_writepnpaddr(0xf0); + vx800_writepnpdata(0x2); + // turn of pnp + vx800_writepnpaddr(0xaa); + + // set up reg to set baud rate. + vx800_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vx800_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vx800_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vx800_writesiobyte(0x3fc, 3); + // Enable interrupts + vx800_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vx800_writesiobyte(0x3f8, 48); + outb(7, 0x80); +} diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c new file mode 100644 index 0000000000..421716cb6c --- /dev/null +++ b/src/northbridge/via/vx800/early_smbus.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "vx800.h" + +#define SMBUS_IO_BASE 0x0500 //from award bios +#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here + +#define SMBHSTSTAT SMBUS_IO_BASE + 0x0 +#define SMBSLVSTAT SMBUS_IO_BASE + 0x1 +#define SMBHSTCTL SMBUS_IO_BASE + 0x2 +#define SMBHSTCMD SMBUS_IO_BASE + 0x3 +#define SMBXMITADD SMBUS_IO_BASE + 0x4 +#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5 +#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6 +/* Rest of these aren't currently used... */ +#define SMBBLKDAT SMBUS_IO_BASE + 0x7 +#define SMBSLVCTL SMBUS_IO_BASE + 0x8 +#define SMBTRNSADD SMBUS_IO_BASE + 0x9 +#define SMBSLVDATA SMBUS_IO_BASE + 0xa +#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe +#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + +#define SMBUS_TIMEOUT (100*1000*10) + +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +#define SMBUS_DELAY() outb(0x80, 0x80) + +#ifdef CONFIG_DEBUG_SMBUS +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX16(x) +#endif + +/* Internal functions */ +static void smbus_print_error(unsigned char host_status_register, int loops) +{ +// print_err("some i2c error\n"); + /* Check if there actually was an error */ + if (host_status_register == 0x00 || host_status_register == 0x40 || + host_status_register == 0x42) + return; + print_err("smbus_error: "); + print_err_hex8(host_status_register); + print_err("\n"); + if (loops >= SMBUS_TIMEOUT) { + print_err("SMBus Timout\n"); + } + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + /* This isn't a real error... */ + print_debug("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } +} + +static void smbus_wait_until_ready(void) +{ + int loops; + + loops = 0; + /* Yes, this is a mess, but it's the easiest way to do it */ + while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { + SMBUS_DELAY(); + ++loops; + } + smbus_print_error(inb(SMBHSTSTAT), loops); +} + +static void smbus_reset(void) +{ + outb(HOST_RESET, SMBHSTSTAT); +} + +/* Public functions */ + +static unsigned int get_spd_data(unsigned int dimm, unsigned int offset) +{ + unsigned int val; + + smbus_reset(); + /* clear host data port */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Do some mathmatic magic */ + dimm = (DIMM0 + dimm) << 1; + + outb(dimm | 0x1, SMBXMITADD); + outb(offset, SMBHSTCMD); + outb(0x48, SMBHSTCTL); + + SMBUS_DELAY(); + + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + smbus_reset(); + return val; +} + +void enable_smbus(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); + + if (dev == PCI_DEV_INVALID) { + /* This won't display text if enable_smbus() is before serial init */ + die("Power Managment Controller not found\n"); + } + + /* Set clock source */ + pci_write_config8(dev, 0x94, 0x20); + + /* Write SMBus IO base to 0xd0, and enable SMBus */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); + + /* Set to Award value */ + pci_write_config8(dev, 0xd2, 0x05); + + /* Make it work for I/O ... */ + pci_write_config16(dev, 0x04, 0x0003); + + smbus_reset(); + /* clear host data port */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); +} + +/** + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * known-good data from a slot/address. Exits on either good data or a timeout. + * + * TODO: This should probably go into some global file, but one would need to + * be created just for it. If some other chip needs/wants it, we can + * worry about it then. + * + * @param mem_ctrl The memory controller and SMBus addresses. + */ +void smbus_fixup(const struct mem_controller *mem_ctrl) +{ + int i, ram_slots, current_slot = 0; + u8 result = 0; + + ram_slots = ARRAY_SIZE(mem_ctrl->channel0); + if (!ram_slots) { + print_err("smbus_fixup() thinks there are no RAM slots!\n"); + return; + } + + PRINT_DEBUG("Waiting for SMBus to warm up"); + + /* + * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for + * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). + * VT8237R has only been seen on DDR and DDR2 based systems, so far. + */ + for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || + (result > + SPD_MEMORY_TYPE_SDRAM_DDR3))); + i++) { + + if (current_slot > ram_slots) + current_slot = 0; + + result = get_spd_data(mem_ctrl->channel0[current_slot], + SPD_MEMORY_TYPE); + current_slot++; + PRINT_DEBUG("."); + } + + if (i >= SMBUS_TIMEOUT) + print_err("SMBus timed out while warming up\n"); + else + PRINT_DEBUG("Done\n"); +} + +/* Debugging Function */ +#if CONFIG_DEBUG_SMBUS +static void dump_spd_data(void) +{ + int dimm, offset, regs; + unsigned int val; + + for (dimm = 0; dimm < 8; dimm++) { + print_debug("SPD Data for DIMM "); + print_debug_hex8(dimm); + print_debug("\n"); + + val = get_spd_data(dimm, 0); + if (val == 0xff) { + regs = 256; + } else if (val == 0x80) { + regs = 128; + } else { + print_debug("No DIMM present\n"); + regs = 0; + } + for (offset = 0; offset < regs; offset++) { + print_debug(" Offset "); + print_debug_hex8(offset); + print_debug(" = 0x"); + print_debug_hex8(get_spd_data(dimm, offset)); + print_debug("\n"); + } + } +} +#else +#define dump_spd_data() +#endif diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c new file mode 100644 index 0000000000..9fa8f35dbe --- /dev/null +++ b/src/northbridge/via/vx800/ide.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "chip.h" +#include +#include "vx800.h" + +static const u8 idedevicepcitable[16 * 12] = { + /* + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6, + 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Legacy BIOS XP PCI value */ + /* + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6, + 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + /* ROM legacy BIOS on cn_8562b */ + /* + 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + /* From legacy BIOS on c7_8562b */ + /* + 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6, + 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ +}; + +static void ide_init(struct device *dev) +{ + u8 i, data; + printk(BIOS_INFO, "ide_init\n"); + + /* these 3 lines help to keep interl back door for DID VID SUBID untouched */ + u16 data16_1, data16_2; + data16_1 = pci_read_config16(dev, 0xba); + data16_2 = pci_read_config16(dev, 0xbe); + + for (i = 0; i < (16 * 12); i++) { + pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]); + } + //pci_write_config8(dev, 0x0d, 0x20); + data = pci_read_config8(dev, 0x0d); + data &= 0x0f; + data |= 0x40; + pci_write_config8(dev, 0x0d, data); + + //these 2 lines help to keep interl back door for DID VID SUBID untouched + pci_write_config16(dev, 0xba, data16_1); + pci_write_config16(dev, 0xbe, data16_2); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); +#if 0 + + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *)dev->chip_info; + + u8 enables; + u32 cablesel; + + pci_write_config16(dev, 0x04, 0x0007); + + enables = pci_read_config8(dev, IDE_CS) & ~0x3; + enables |= 0x02; + pci_write_config8(dev, IDE_CS, enables); + enables = pci_read_config8(dev, IDE_CS); + printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); + + /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, IDE_CONF_II); + enables &= ~0xc0; + pci_write_config8(dev, IDE_CONF_II, enables); + enables = pci_read_config8(dev, IDE_CONF_II); + printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); + + /* Enable prefetch buffers. */ + enables = pci_read_config8(dev, IDE_CONF_I); + enables |= 0xf0; + pci_write_config8(dev, IDE_CONF_I, enables); + + /* Flush FIFOs at half. */ + enables = pci_read_config8(dev, IDE_CONF_FIFO); + enables &= 0xf0; + enables |= (1 << 2) | (1 << 0); + pci_write_config8(dev, IDE_CONF_FIFO, enables); + + /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ + enables = pci_read_config8(dev, IDE_MISC_I); + enables &= 0xe2; + enables |= (1 << 4) | (1 << 3); + pci_write_config8(dev, IDE_MISC_I, enables); + + /* Use memory read multiple, Memory-Write-and-Invalidate. */ + enables = pci_read_config8(dev, IDE_MISC_II); + enables |= (1 << 2) | (1 << 3); + pci_write_config8(dev, IDE_MISC_II, enables); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Cable guy... */ + cablesel = pci_read_config32(dev, IDE_UDMA); + cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); + cablesel |= (sb->ide0_80pin_cable << 28) | + (sb->ide0_80pin_cable << 20) | + (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); + pci_write_config32(dev, IDE_UDMA, cablesel); +#endif +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver via_ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX855_IDE, +}; diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c new file mode 100644 index 0000000000..b9941d1270 --- /dev/null +++ b/src/northbridge/via/vx800/lpc.c @@ -0,0 +1,377 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "vx800.h" +#include "chip.h" + +static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa }; + +static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA + +static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4 + +static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA +static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA +static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA +static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA +static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA + +static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 + +static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char Irqs[4]; + int i; + for (i = 0; i < 4; i++) + Irqs[i] = pciIrqs[pin[i] - 'A']; + + return Irqs; +} + +static void pci_routing_fixup(struct device *dev) +{ + printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev); + + /* set up PCI IRQ routing */ + pci_write_config8(dev, 0x55, pciIrqs[0] << 4); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4)); + pci_write_config8(dev, 0x57, pciIrqs[3] << 4); + + /* VGA */ + printk(BIOS_INFO, "setting vga\n"); + pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting pci slot\n"); + pci_assign_irqs(0, 0x08, pin_to_irq(slotPins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting USB Device Controller\n"); + pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting SDIO Controller\n"); + pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting SD $ MS Controller\n"); + pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n"); + pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins)); + + /* PCI slot */ + printk(BIOS_INFO, "setting ide\n"); + //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins)); + + /* Standard usb components */ + printk(BIOS_INFO, "setting usb1-2\n"); +// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); + + /* sound hardware */ + printk(BIOS_INFO, "setting hdac audio\n"); + pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins)); + + printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); +} + +static void setup_pm(device_t dev) +{ + u16 tmp; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to IO VX800_ACPI_IO_BASE */ + pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1); + + /* set ACPI irq to 9 */ + pci_write_config8(dev, 0x82, 0x49); + + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ +// pci_write_config16(dev, 0x84, 0x30f2); + pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? + + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* Power Well */ + pci_write_config8(dev, 0x94, 0x20); // 0x20?? + + /* 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + */ + pci_write_config8(dev, 0x95, 0xc0); // 0xc1?? + + /* Disable GP2 & GP3 Timer */ + pci_write_config8(dev, 0x98, 0); + + /* GP2 Timer Counter */ + pci_write_config8(dev, 0x99, 0xfb); + /* GP3 Timer Counter */ + //pci_write_config8(dev, 0x9a, 0x20); + + /* Multi Function Select 1 */ + pci_write_config8(dev, 0xe4, 0x00); + /* Multi Function Select 2 */ + pci_write_config8(dev, 0xe5, 0x41); //?? + + /* Enable ACPI access (and setup like award) */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, VX800_ACPI_IO_BASE + 0x00); + outw(0xffff, VX800_ACPI_IO_BASE + 0x20); + outw(0xffff, VX800_ACPI_IO_BASE + 0x28); + outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, VX800_ACPI_IO_BASE + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, VX800_ACPI_IO_BASE + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, VX800_ACPI_IO_BASE + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, VX800_ACPI_IO_BASE + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, VX800_ACPI_IO_BASE + 0x34); + + /* GP timer reload on none. */ + outl(0x0, VX800_ACPI_IO_BASE + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, VX800_ACPI_IO_BASE + 0x42); + + tmp = inw(VX800_ACPI_IO_BASE + 0x04); + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + tmp |= 1; + outw(tmp, VX800_ACPI_IO_BASE + 0x04); + + /* Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VX800_ACPI_IO_BASE + 0x11); +/* + outw(0x0, 0x424); + outw(0x0, 0x42a); + outw(0x1, 0x42c); + outl(0x0, 0x434); + outl(0x01, 0x438); + outb(0x0, 0x442); + outl(0xffff7fff, 0x448); + outw(0x001, 0x404); +*/ +} + +static void S3_ps2_kb_ms_wakeup(struct device *dev) +{ + u8 enables; + enables = pci_read_config8(dev, 0x51); + enables |= 2; + pci_write_config8(dev, 0x51, enables); + + outb(0xe0, 0x2e); + outb(0x0b, 0x2f); //if 09,then only support kb wakeup + + outb(0xe1, 0x2e); //set any key scan code can wakeup + outb(0x00, 0x2f); + + outb(0xe9, 0x2e); //set any mouse scan code can wakeup + outb(0x00, 0x2f); + + enables &= 0xd; + pci_write_config8(dev, 0x51, enables); + + outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME + +} + +static void S3_usb_wakeup(struct device *dev) +{ + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME +} + +static void S3_lid_wakeup(struct device *dev) +{ + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME +} + +/* This looks good enough to work, maybe */ +static void vx800_sb_init(struct device *dev) +{ + unsigned char enables; + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + // Map 4MB of FLASH into the address space +// pci_write_config8(dev, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* DMA Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf0; + pci_write_config8(dev, 0x42, enables); + + /* I/O recovery time */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* Set 0x5b to 0x01 to match Award */ + //pci_write_config8(dev, 0x5b, 0x01); + enables = pci_read_config8(dev, 0x5b); + enables |= 0x01; + pci_write_config8(dev, 0x5b, enables); + + /* Set Read Pass Write Control Enable */ + pci_write_config8(dev, 0x48, 0x0c); + + /* Set 0x58 to 0x42 APIC and RTC. */ + //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. + enables = pci_read_config8(dev, 0x58); + enables |= 0x41; // + pci_write_config8(dev, 0x58, enables); + + /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + /* enable serial irq */ + pci_write_config8(dev, 0x52, 0x9); + + /* dma */ + pci_write_config8(dev, 0x53, 0x00); + + // Power management setup + setup_pm(dev); + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev, 0x40, 0x54); + + // Start the rtc + rtc_init(0); +} + +/* total kludge to get lxb to call our childrens set/enable functions - these are + not called unless this device has a resource to set - so set a dummy one */ +static void vx800_read_resources(device_t dev) +{ + + struct resource *resource; + pci_dev_read_resources(dev); + resource = new_resource(dev, 1); + resource->flags |= + IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | + IORESOURCE_STORED; + resource->size = 2; + resource->base = 0x2e; +} + +static void vx800_set_resources(device_t dev) +{ + struct resource *resource; + resource = find_resource(dev, 1); + resource->flags |= IORESOURCE_STORED; + pci_dev_set_resources(dev); +} + +static void southbridge_init(struct device *dev) +{ + printk(BIOS_DEBUG, "vx800 sb init\n"); + vx800_sb_init(dev); + pci_routing_fixup(dev); + + setup_i8259(); // make sure interupt controller is configured before keyboard init + + /* turn on keyboard and RTC, no need to visit this reg twice */ + pc_keyboard_init(0); + + printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); + S3_ps2_kb_ms_wakeup(dev); + S3_usb_wakeup(dev); + S3_lid_wakeup(dev); + +/* enable acpi cpu c3 state. (c2 state need not do anything.) + #1 + fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 + fadt->p_lvl2_lat = 0x50; //this is the coreboot source + fadt->p_lvl3_lat = 0x320;// + fadt->pm2_cnt_len = 1;//to support cpu-c3 + #2 + ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) + #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. + 1 enable SLP# asserts in C3 state PMIORx26<1> =1 + 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 + 3 CLKRUN# is always asserted PMIORx26<3> =0 + 4 Disable PCISTP# When CLKRUN# is asserted + 1: PCISTP# will not assert When CLKRUN# is asserted + PMIORx26<4> =1 + 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. + VRDSLP will be active in either this bit set in C3 or LVL4 register read + PMIORx26<0> =0 + 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 + */ + outb(0x17, VX800_ACPI_IO_BASE + 0x26); + +} + +static struct device_operations vx800_lpc_ops = { + .read_resources = vx800_read_resources, + .set_resources = vx800_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = southbridge_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &vx800_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX855_LPC, +}; diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c index ce9b7d4fab..f039b025ff 100644 --- a/src/northbridge/via/vx800/raminit.c +++ b/src/northbridge/via/vx800/raminit.c @@ -35,8 +35,8 @@ #endif #include "northbridge/via/vx800/translator_ddr2_init.c" #include "northbridge/via/vx800/dram_init.h" -#include "northbridge/via/vx800/vx800_early_smbus.c" -#include "northbridge/via/vx800/vx800_early_serial.c" +#include "northbridge/via/vx800/early_smbus.c" +#include "northbridge/via/vx800/early_serial.c" #include "northbridge/via/vx800/dram_util.h" #include "northbridge/via/vx800/dram_util.c" #include "northbridge/via/vx800/detection.c" diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c deleted file mode 100644 index f46341ff15..0000000000 --- a/src/northbridge/via/vx800/vx800_early_serial.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -/* - * Enable the serial devices on the VIA - */ -#include - -/* The base address is 0x15c, 0x2e, depending on config bytes */ - -#define SIO_BASE 0x3f0 -#define SIO_DATA SIO_BASE+1 - -static void vx800_writepnpaddr(uint8_t val) -{ - outb(val, 0x2e); - outb(val, 0xeb); -} - -static void vx800_writepnpdata(uint8_t val) -{ - outb(val, 0x2f); - outb(val, 0xeb); -} - -static void vx800_writesiobyte(uint16_t reg, uint8_t val) -{ - outb(val, reg); -} - -static void vx800_writesioword(uint16_t reg, uint16_t val) -{ - outw(val, reg); -} - -/* regs we use: 85, and the southbridge devfn is defined by the - mainboard - */ - -void enable_vx800_serial(void) -{ - outb(6, 0x80); - outb(0x03, 0x22); - - //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); - //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10); - - // turn on pnp - vx800_writepnpaddr(0x87); - vx800_writepnpaddr(0x87); - // now go ahead and set up com1. - // set address - vx800_writepnpaddr(0x7); - vx800_writepnpdata(0x2); - // enable serial out - vx800_writepnpaddr(0x30); - vx800_writepnpdata(0x1); - // serial port 1 base address (FEh) - vx800_writepnpaddr(0x60); - vx800_writepnpdata(0xfe); - // serial port 1 IRQ (04h) - vx800_writepnpaddr(0x70); - vx800_writepnpdata(0x4); - // serial port 1 control - vx800_writepnpaddr(0xf0); - vx800_writepnpdata(0x2); - // turn of pnp - vx800_writepnpaddr(0xaa); - - // set up reg to set baud rate. - vx800_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vx800_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vx800_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vx800_writesiobyte(0x3fc, 3); - // Enable interrupts - vx800_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vx800_writesiobyte(0x3f8, 48); - outb(7, 0x80); -} diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c deleted file mode 100644 index 421716cb6c..0000000000 --- a/src/northbridge/via/vx800/vx800_early_smbus.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "vx800.h" - -#define SMBUS_IO_BASE 0x0500 //from award bios -#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here - -#define SMBHSTSTAT SMBUS_IO_BASE + 0x0 -#define SMBSLVSTAT SMBUS_IO_BASE + 0x1 -#define SMBHSTCTL SMBUS_IO_BASE + 0x2 -#define SMBHSTCMD SMBUS_IO_BASE + 0x3 -#define SMBXMITADD SMBUS_IO_BASE + 0x4 -#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5 -#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6 -/* Rest of these aren't currently used... */ -#define SMBBLKDAT SMBUS_IO_BASE + 0x7 -#define SMBSLVCTL SMBUS_IO_BASE + 0x8 -#define SMBTRNSADD SMBUS_IO_BASE + 0x9 -#define SMBSLVDATA SMBUS_IO_BASE + 0xa -#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe -#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf - -/* Define register settings */ -#define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ - -#define SMBUS_TIMEOUT (100*1000*10) - -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 - -#define SMBUS_DELAY() outb(0x80, 0x80) - -#ifdef CONFIG_DEBUG_SMBUS -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) -#else -#define PRINT_DEBUG(x) -#define PRINT_DEBUG_HEX16(x) -#endif - -/* Internal functions */ -static void smbus_print_error(unsigned char host_status_register, int loops) -{ -// print_err("some i2c error\n"); - /* Check if there actually was an error */ - if (host_status_register == 0x00 || host_status_register == 0x40 || - host_status_register == 0x42) - return; - print_err("smbus_error: "); - print_err_hex8(host_status_register); - print_err("\n"); - if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\n"); - } - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } -} - -static void smbus_wait_until_ready(void) -{ - int loops; - - loops = 0; - /* Yes, this is a mess, but it's the easiest way to do it */ - while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { - SMBUS_DELAY(); - ++loops; - } - smbus_print_error(inb(SMBHSTSTAT), loops); -} - -static void smbus_reset(void) -{ - outb(HOST_RESET, SMBHSTSTAT); -} - -/* Public functions */ - -static unsigned int get_spd_data(unsigned int dimm, unsigned int offset) -{ - unsigned int val; - - smbus_reset(); - /* clear host data port */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* Do some mathmatic magic */ - dimm = (DIMM0 + dimm) << 1; - - outb(dimm | 0x1, SMBXMITADD); - outb(offset, SMBHSTCMD); - outb(0x48, SMBHSTCTL); - - SMBUS_DELAY(); - - smbus_wait_until_ready(); - - val = inb(SMBHSTDAT0); - smbus_reset(); - return val; -} - -void enable_smbus(void) -{ - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); - - if (dev == PCI_DEV_INVALID) { - /* This won't display text if enable_smbus() is before serial init */ - die("Power Managment Controller not found\n"); - } - - /* Set clock source */ - pci_write_config8(dev, 0x94, 0x20); - - /* Write SMBus IO base to 0xd0, and enable SMBus */ - pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); - - /* Set to Award value */ - pci_write_config8(dev, 0xd2, 0x05); - - /* Make it work for I/O ... */ - pci_write_config16(dev, 0x04, 0x0003); - - smbus_reset(); - /* clear host data port */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); -} - -/** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for - * known-good data from a slot/address. Exits on either good data or a timeout. - * - * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. - * - * @param mem_ctrl The memory controller and SMBus addresses. - */ -void smbus_fixup(const struct mem_controller *mem_ctrl) -{ - int i, ram_slots, current_slot = 0; - u8 result = 0; - - ram_slots = ARRAY_SIZE(mem_ctrl->channel0); - if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\n"); - return; - } - - PRINT_DEBUG("Waiting for SMBus to warm up"); - - /* - * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for - * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). - * VT8237R has only been seen on DDR and DDR2 based systems, so far. - */ - for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > - SPD_MEMORY_TYPE_SDRAM_DDR3))); - i++) { - - if (current_slot > ram_slots) - current_slot = 0; - - result = get_spd_data(mem_ctrl->channel0[current_slot], - SPD_MEMORY_TYPE); - current_slot++; - PRINT_DEBUG("."); - } - - if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\n"); - else - PRINT_DEBUG("Done\n"); -} - -/* Debugging Function */ -#if CONFIG_DEBUG_SMBUS -static void dump_spd_data(void) -{ - int dimm, offset, regs; - unsigned int val; - - for (dimm = 0; dimm < 8; dimm++) { - print_debug("SPD Data for DIMM "); - print_debug_hex8(dimm); - print_debug("\n"); - - val = get_spd_data(dimm, 0); - if (val == 0xff) { - regs = 256; - } else if (val == 0x80) { - regs = 128; - } else { - print_debug("No DIMM present\n"); - regs = 0; - } - for (offset = 0; offset < regs; offset++) { - print_debug(" Offset "); - print_debug_hex8(offset); - print_debug(" = 0x"); - print_debug_hex8(get_spd_data(dimm, offset)); - print_debug("\n"); - } - } -} -#else -#define dump_spd_data() -#endif diff --git a/src/northbridge/via/vx800/vx800_ide.c b/src/northbridge/via/vx800/vx800_ide.c deleted file mode 100644 index 9fa8f35dbe..0000000000 --- a/src/northbridge/via/vx800/vx800_ide.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "chip.h" -#include -#include "vx800.h" - -static const u8 idedevicepcitable[16 * 12] = { - /* - 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, - 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6, - 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - */ - - 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, - 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - /* Legacy BIOS XP PCI value */ - /* - 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, - 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6, - 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - */ - - /* ROM legacy BIOS on cn_8562b */ - /* - 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, - 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - */ - - /* From legacy BIOS on c7_8562b */ - /* - 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, - 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6, - 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - */ -}; - -static void ide_init(struct device *dev) -{ - u8 i, data; - printk(BIOS_INFO, "ide_init\n"); - - /* these 3 lines help to keep interl back door for DID VID SUBID untouched */ - u16 data16_1, data16_2; - data16_1 = pci_read_config16(dev, 0xba); - data16_2 = pci_read_config16(dev, 0xbe); - - for (i = 0; i < (16 * 12); i++) { - pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]); - } - //pci_write_config8(dev, 0x0d, 0x20); - data = pci_read_config8(dev, 0x0d); - data &= 0x0f; - data |= 0x40; - pci_write_config8(dev, 0x0d, data); - - //these 2 lines help to keep interl back door for DID VID SUBID untouched - pci_write_config16(dev, 0xba, data16_1); - pci_write_config16(dev, 0xbe, data16_2); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); -#if 0 - - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - - u8 enables; - u32 cablesel; - - pci_write_config16(dev, 0x04, 0x0007); - - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= 0x02; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); - cablesel |= (sb->ide0_80pin_cable << 28) | - (sb->ide0_80pin_cable << 20) | - (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); - pci_write_config32(dev, IDE_UDMA, cablesel); -#endif -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver via_ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX855_IDE, -}; diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c deleted file mode 100644 index b9941d1270..0000000000 --- a/src/northbridge/via/vx800/vx800_lpc.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "vx800.h" -#include "chip.h" - -static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa }; - -static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA - -static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4 - -static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA -static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA -static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA -static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA -static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA - -static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 - -static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0; i < 4; i++) - Irqs[i] = pciIrqs[pin[i] - 'A']; - - return Irqs; -} - -static void pci_routing_fixup(struct device *dev) -{ - printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev); - - /* set up PCI IRQ routing */ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4)); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - /* VGA */ - printk(BIOS_INFO, "setting vga\n"); - pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting pci slot\n"); - pci_assign_irqs(0, 0x08, pin_to_irq(slotPins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting USB Device Controller\n"); - pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting SDIO Controller\n"); - pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting SD $ MS Controller\n"); - pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n"); - pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins)); - - /* PCI slot */ - printk(BIOS_INFO, "setting ide\n"); - //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins)); - - /* Standard usb components */ - printk(BIOS_INFO, "setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - /* sound hardware */ - printk(BIOS_INFO, "setting hdac audio\n"); - pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins)); - - printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); -} - -static void setup_pm(device_t dev) -{ - u16 tmp; - /* Debounce LID and PWRBTN# Inputs for 16ms. */ - pci_write_config8(dev, 0x80, 0x20); - - /* Set ACPI base address to IO VX800_ACPI_IO_BASE */ - pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1); - - /* set ACPI irq to 9 */ - pci_write_config8(dev, 0x82, 0x49); - - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ -// pci_write_config16(dev, 0x84, 0x30f2); - pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? - - /* SMI output level to low, 7.5us throttle clock */ - pci_write_config8(dev, 0x8d, 0x18); - - /* GP Timer Control 1s */ - pci_write_config8(dev, 0x93, 0x88); - - /* Power Well */ - pci_write_config8(dev, 0x94, 0x20); // 0x20?? - - /* 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - */ - pci_write_config8(dev, 0x95, 0xc0); // 0xc1?? - - /* Disable GP2 & GP3 Timer */ - pci_write_config8(dev, 0x98, 0); - - /* GP2 Timer Counter */ - pci_write_config8(dev, 0x99, 0xfb); - /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); - - /* Multi Function Select 1 */ - pci_write_config8(dev, 0xe4, 0x00); - /* Multi Function Select 2 */ - pci_write_config8(dev, 0xe5, 0x41); //?? - - /* Enable ACPI access (and setup like award) */ - pci_write_config8(dev, 0x81, 0x84); - - /* Clear status events. */ - outw(0xffff, VX800_ACPI_IO_BASE + 0x00); - outw(0xffff, VX800_ACPI_IO_BASE + 0x20); - outw(0xffff, VX800_ACPI_IO_BASE + 0x28); - outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30); - - /* Disable SCI on GPIO. */ - outw(0x0, VX800_ACPI_IO_BASE + 0x22); - - /* Disable SMI on GPIO. */ - outw(0x0, VX800_ACPI_IO_BASE + 0x24); - - /* Disable all global enable SMIs. */ - outw(0x0, VX800_ACPI_IO_BASE + 0x2a); - - /* All SMI off, both IDE buses ON, PSON rising edge. */ - outw(0x0, VX800_ACPI_IO_BASE + 0x2c); - - /* Primary activity SMI disable. */ - outl(0x0, VX800_ACPI_IO_BASE + 0x34); - - /* GP timer reload on none. */ - outl(0x0, VX800_ACPI_IO_BASE + 0x38); - - /* Disable extended IO traps. */ - outb(0x0, VX800_ACPI_IO_BASE + 0x42); - - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - /* SCI is generated for RTC/pwrBtn/slpBtn. */ - tmp |= 1; - outw(tmp, VX800_ACPI_IO_BASE + 0x04); - - /* Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VX800_ACPI_IO_BASE + 0x11); -/* - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -*/ -} - -static void S3_ps2_kb_ms_wakeup(struct device *dev) -{ - u8 enables; - enables = pci_read_config8(dev, 0x51); - enables |= 2; - pci_write_config8(dev, 0x51, enables); - - outb(0xe0, 0x2e); - outb(0x0b, 0x2f); //if 09,then only support kb wakeup - - outb(0xe1, 0x2e); //set any key scan code can wakeup - outb(0x00, 0x2f); - - outb(0xe9, 0x2e); //set any mouse scan code can wakeup - outb(0x00, 0x2f); - - enables &= 0xd; - pci_write_config8(dev, 0x51, enables); - - outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger - outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME - -} - -static void S3_usb_wakeup(struct device *dev) -{ - outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME -} - -static void S3_lid_wakeup(struct device *dev) -{ - outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME -} - -/* This looks good enough to work, maybe */ -static void vx800_sb_init(struct device *dev) -{ - unsigned char enables; - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); - - /* DMA Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - /* I/O recovery time */ - pci_write_config8(dev, 0x4c, 0x44); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* Set 0x5b to 0x01 to match Award */ - //pci_write_config8(dev, 0x5b, 0x01); - enables = pci_read_config8(dev, 0x5b); - enables |= 0x01; - pci_write_config8(dev, 0x5b, enables); - - /* Set Read Pass Write Control Enable */ - pci_write_config8(dev, 0x48, 0x0c); - - /* Set 0x58 to 0x42 APIC and RTC. */ - //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. - enables = pci_read_config8(dev, 0x58); - enables |= 0x41; // - pci_write_config8(dev, 0x58, enables); - - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - /* enable serial irq */ - pci_write_config8(dev, 0x52, 0x9); - - /* dma */ - pci_write_config8(dev, 0x53, 0x00); - - // Power management setup - setup_pm(dev); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - - // Start the rtc - rtc_init(0); -} - -/* total kludge to get lxb to call our childrens set/enable functions - these are - not called unless this device has a resource to set - so set a dummy one */ -static void vx800_read_resources(device_t dev) -{ - - struct resource *resource; - pci_dev_read_resources(dev); - resource = new_resource(dev, 1); - resource->flags |= - IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | - IORESOURCE_STORED; - resource->size = 2; - resource->base = 0x2e; -} - -static void vx800_set_resources(device_t dev) -{ - struct resource *resource; - resource = find_resource(dev, 1); - resource->flags |= IORESOURCE_STORED; - pci_dev_set_resources(dev); -} - -static void southbridge_init(struct device *dev) -{ - printk(BIOS_DEBUG, "vx800 sb init\n"); - vx800_sb_init(dev); - pci_routing_fixup(dev); - - setup_i8259(); // make sure interupt controller is configured before keyboard init - - /* turn on keyboard and RTC, no need to visit this reg twice */ - pc_keyboard_init(0); - - printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); - S3_ps2_kb_ms_wakeup(dev); - S3_usb_wakeup(dev); - S3_lid_wakeup(dev); - -/* enable acpi cpu c3 state. (c2 state need not do anything.) - #1 - fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 - fadt->p_lvl2_lat = 0x50; //this is the coreboot source - fadt->p_lvl3_lat = 0x320;// - fadt->pm2_cnt_len = 1;//to support cpu-c3 - #2 - ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) - #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. - 1 enable SLP# asserts in C3 state PMIORx26<1> =1 - 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 - 3 CLKRUN# is always asserted PMIORx26<3> =0 - 4 Disable PCISTP# When CLKRUN# is asserted - 1: PCISTP# will not assert When CLKRUN# is asserted - PMIORx26<4> =1 - 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. - VRDSLP will be active in either this bit set in C3 or LVL4 register read - PMIORx26<0> =0 - 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 - */ - outb(0x17, VX800_ACPI_IO_BASE + 0x26); - -} - -static struct device_operations vx800_lpc_ops = { - .read_resources = vx800_read_resources, - .set_resources = vx800_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vx800_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX855_LPC, -}; -- cgit v1.2.3