From 08c92e03bf46e40559a25062fc77258c0eff2efb Mon Sep 17 00:00:00 2001 From: Kerry She Date: Sat, 4 Sep 2010 06:13:02 +0000 Subject: AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. Signed-off-by: Kerry She Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct/mct_d.c | 3 ++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index c56576aa6c..afeb4e98d2 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3461,9 +3461,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, i = 0; /* use i for the dct setting required */ if (pDCTstat->MAdimms[0] < 4) i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) + if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { dword &= 0xF18FFF18; index_reg = 0x98; /* force dct = 0 */ + } } Set_NB32_index_wait(dev, index_reg, 0x0a, dword); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0e187621b4..09ade32f46 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3127,9 +3127,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, i = 0; /* use i for the dct setting required */ if (pDCTstat->MAdimms[0] < 4) i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) + if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { dword &= 0xF18FFF18; index_reg = 0x98; /* force dct = 0 */ + } } Set_NB32_index_wait(dev, index_reg, 0x0a, dword); -- cgit v1.2.3