From 266a1f794dc28053e97794cbeb3f1a588137698b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 9 Jun 2016 18:13:34 +0200 Subject: nb/intel/raminit (native): Read PCI mmio size from devicetree Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/gm45/chip.h | 5 +++++ src/northbridge/intel/gm45/raminit.c | 24 +++++++++++++++++++++++- src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/nehalem/raminit.c | 26 +++++++++++++++++++++++++- src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/intel/sandybridge/raminit.c | 21 ++++++++++++++++++++- 6 files changed, 83 insertions(+), 3 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index b537b93633..836d6bb737 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,11 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index ab54abc754..37b44cc763 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -20,11 +20,13 @@ #include #include #include +#include #include #include #include #include "delay.h" #include "gm45.h" +#include "chip.h" static const gmch_gfx_t gmch_gfx_types[][5] = { /* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ @@ -1156,6 +1158,25 @@ static void vc1_program_timings(const fsb_clock_t fsb) EPBAR32(0x3c) = timings_by_fsb[fsb][1]; } +#define DEFAULT_PCI_MMIO_SIZE 2048 +#define HOST_BRIDGE PCI_DEVFN(0, 0) + +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_gm45_config *cfg = NULL; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + /* @prejedec if not zero, set rank size to 128MB and page size to 4KB. */ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode_t mode, const int prejedec, u16 ggc) { @@ -1226,7 +1247,8 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode } } - const unsigned int MMIOstart = 0x0c00 + uma_sizem; /* 3GB, makes MTRR configuration small. */ + const unsigned int mmio_size = get_mmio_size(); + const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem; const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index caf98196bd..a9d136baad 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -41,6 +41,11 @@ struct northbridge_intel_nehalem_config { u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 0549de766a..69e7108271 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -32,10 +32,12 @@ #include #include #include +#include #include #include #include #include "raminit.h" +#include "chip.h" #include #include #include @@ -1450,6 +1452,25 @@ static void program_board_delay(struct raminfo *info) } } +#define DEFAULT_PCI_MMIO_SIZE 2048 +#define HOST_BRIDGE PCI_DEVFN(0, 0) + +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_nehalem_config *cfg = NULL; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + #define BETTER_MEMORY_MAP 0 static void program_total_memory_map(struct raminfo *info) @@ -1459,6 +1480,7 @@ static void program_total_memory_map(struct raminfo *info) unsigned int REMAPbase; unsigned int uma_base_igd; unsigned int uma_base_gtt; + unsigned int mmio_size; int memory_remap; unsigned int memory_map[8]; int i; @@ -1485,11 +1507,13 @@ static void program_total_memory_map(struct raminfo *info) } #endif + mmio_size = get_mmio_size(); + TOM = info->total_memory_mb; if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(3072 + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 5effc0da95..d002824287 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -47,6 +47,11 @@ struct northbridge_intel_sandybridge_config { u16 max_mem_clock_mhz; struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6bb77b2c6a..4563547c79 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -204,6 +204,7 @@ typedef struct ramctr_timing_st { #define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); +static unsigned int get_mmio_size(void); static const char *ecc_decoder[] = { "inactive", @@ -1086,7 +1087,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) size_t tsegbasedelta, remapbase, remaplimit; uint16_t ggc; - mmiosize = 0x400; + mmiosize = get_mmio_size(); ggc = pci_read_config16(NORTHBRIDGE, GGC); if (!(ggc & 2)) { @@ -4384,6 +4385,24 @@ static unsigned int get_mem_min_tck(void) } } +#define DEFAULT_PCI_MMIO_SIZE 2048 + +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_sandybridge_config *cfg = NULL; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + void perform_raminit(int s3resume) { spd_raw_data spd[4]; -- cgit v1.2.3