From 39a6093d7937dec85077f754fbcaa2e2be493eae Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 4 Jul 2020 01:07:24 +0200 Subject: haswell: Automatically check if Intel GbE is to be enabled If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC to enable it as well. No one can ever forget to set this option anymore! Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128 Reviewed-by: Nico Huber Reviewed-by: Tristan Corrick Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 2961299e7d..7016fd9a7e 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +38,8 @@ static int make_channel_disabled_mask(const struct pei_data *pd, int ch) /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { + const struct device *gbe = pcidev_on_root(0x19, 0); + int wake_from_s3; struct pei_data pei_data = { @@ -53,6 +56,7 @@ void mainboard_romstage_entry(void) .temp_mmio_base = 0xfed08000, .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, + .gbe_enable = gbe && gbe->enabled, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, }; -- cgit v1.2.3