From 540151f115c965472ae0d30bce9c12e93cbc7c01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 15 Aug 2019 11:20:18 +0300 Subject: intel/haswell: Use smm_subregion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/memmap.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 5bc74f8703..b1eb770f90 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -20,9 +20,9 @@ #include #include #include +#include #include #include -#include #include "haswell.h" static uintptr_t smm_region_start(void) @@ -40,17 +40,10 @@ void *cbmem_top(void) return (void *)smm_region_start(); } -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) - -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *start = smm_region_start(); + *size = CONFIG_SMM_TSEG_SIZE; } void fill_postcar_frame(struct postcar_frame *pcf) -- cgit v1.2.3