From 551cff08d540ced6817cfe230750a311d573c209 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 10 Oct 2015 23:58:08 +0200 Subject: Derive lvds_dual_channel from EDID timings. Based on the info by Felix Held. Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/11857 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/gm45/gma.c | 14 +++++++------- src/northbridge/intel/i945/chip.h | 1 - src/northbridge/intel/i945/gma.c | 10 +++++----- src/northbridge/intel/nehalem/gma.c | 14 +++++++------- src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 17 +++++++++-------- .../intel/sandybridge/gma_sandybridge_lvds.c | 14 +++++++------- 6 files changed, 35 insertions(+), 35 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 42b340a8b8..33eae84774 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -174,7 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = mode->hso; vfront_porch = mode->vso; - target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock + target_frequency = mode->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_sr_write(1, 1); @@ -259,7 +259,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -276,7 +276,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -287,7 +287,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) @@ -295,7 +295,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) @@ -306,7 +306,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -397,7 +397,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 57060869e4..52925ff7fd 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,6 +4,5 @@ struct northbridge_intel_i945_config { u32 gpu_hotplug; u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; - int gpu_lvds_is_dual_channel; struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8b70e55cf2..824e69e1e7 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -162,7 +162,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = conf->gpu_lvds_is_dual_channel ? mode->pixel_clock + target_frequency = mode->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); /* Find suitable divisors. */ @@ -212,7 +212,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel + printk(BIOS_DEBUG, (mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", @@ -251,7 +251,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV @@ -262,7 +262,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) | (pixel_p1 << 16) @@ -318,7 +318,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); write32(pmmio + LVDS, LVDS_ON | (hpolarity << 20) | (vpolarity << 21) - | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_A_POWERUP_ALL | LVDS_PIPE(1)); diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 9abbdea5c9..ed993f1270 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -722,7 +722,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = mode->hso; vfront_porch = mode->vso; - target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock + target_frequency = mode->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); vga_textmode_init(); #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) @@ -807,7 +807,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -824,7 +824,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -839,7 +839,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) @@ -847,7 +847,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) @@ -858,7 +858,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -955,7 +955,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 101a3c11d3..7cb71f3713 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -231,8 +231,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->lvds_dual_channel ? edid.mode.pixel_clock - : (2 * edid.mode.pixel_clock); + u32 target_frequency = ( + edid.mode.lvds_dual_channel ? edid.mode.pixel_clock + : (2 * edid.mode.pixel_clock)); u32 pixel_p1 = 1; u32 pixel_n = 1; u32 pixel_m1 = 1; @@ -327,7 +328,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + edid.mode.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -344,7 +345,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -359,7 +360,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) @@ -371,7 +372,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) @@ -382,7 +383,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -482,7 +483,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 758a41d83f..9b2f1f2225 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -205,7 +205,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, hfront_porch = mode->hso; vfront_porch = mode->vso; - target_frequency = info->lvds_dual_channel ? mode->pixel_clock + target_frequency = mode->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { @@ -291,7 +291,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -308,7 +308,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -324,7 +324,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) @@ -332,7 +332,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) @@ -343,7 +343,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -441,7 +441,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); -- cgit v1.2.3