From 8e23bac97ec66a49f9ddb1a4069e4e68666833fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 17 Aug 2019 06:47:50 +0300 Subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 04a696c2c2..43e71f4d3d 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -26,12 +26,6 @@ #include #include "../chip.h" -#ifdef __PRE_RAM__ -#include -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -96,9 +90,9 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if CONFIG(ENABLE_FSP_FAST_BOOT) - UpdData->PcdFastboot = UPD_ENABLE; -#endif + if (CONFIG(ENABLE_FSP_FAST_BOOT)) + UpdData->PcdFastboot = UPD_ENABLE; + /* * Loop through all the SOC devices in the devicetree * enabling and disabling them as requested. @@ -164,5 +158,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ -- cgit v1.2.3